[PATCH] D60177: [PowerPC] initialize SchedModel according to platform

[ChenZheng via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL357962: [PowerPC] initialize SchedModel according to platform. (authored by shchenz, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D60177?vs=193428&id=194231#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60177/new/

https://reviews.llvm.org/D60177

Files:
  llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
  llvm/trunk/test/CodeGen/PowerPC/ctrloop-shortLoops.ll


Index: llvm/trunk/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
+++ llvm/trunk/test/CodeGen/PowerPC/ctrloop-shortLoops.ll
@@ -122,7 +122,7 @@
 ; a2q should use mtctr, but pwr8 should not use mtctr.
 define signext i32 @testTripCount5() {
 ; CHECK-LABEL: testTripCount5:
-; CHECK-PWR8: mtctr
+; CHECK-PWR8-NOT: mtctr
 ; CHECK-A2Q: mtctr
  
 entry:
Index: llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCCTRLoops.cpp
@@ -202,6 +202,7 @@
   auto *TLIP = getAnalysisIfAvailable<TargetLibraryInfoWrapperPass>();
   LibInfo = TLIP ? &TLIP->getTLI() : nullptr;
   PreserveLCSSA = mustPreserveAnalysisID(LCSSAID);
+  SchedModel.init(STI);
 
   bool MadeChange = false;
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D60177.194231.patch
Type: text/x-patch
Size: 939 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190409/21b87721/attachment.bin>