[PATCH] D60433: [AArch64][GlobalISel] Add legalization for some vector G_LSR and G_ASHR

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added a reviewer: paquette.
aemerson added a project: LLVM.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.

This is needed for some future support for vector ICMP.

Also make G_TRUNC always legal as we need it as a legalization artifact, and the current legacy rules don't cover some vector types.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60433

Files:
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -160,7 +160,7 @@
 # DEBUG:      .. the first uncovered type index: 2, OK
 #
 # DEBUG-NEXT: G_TRUNC (opcode {{[0-9]+}}): 2 type indices
-# DEBUG:      .. type index coverage check SKIPPED: no rules defined
+# DEBUG:      .. type index coverage check SKIPPED: user-defined predicate detected
 #
 # DEBUG-NEXT: G_CONSTANT (opcode {{[0-9]+}}): 1 type index
 # DEBUG:      .. the first uncovered type index: 1, OK
Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -202,3 +202,34 @@
     $q0 = COPY %2
 
 ...
+
+---
+name: test_ashr_v2i32
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_ashr_v2i32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
+    ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[COPY1]](<2 x s32>)
+    ; CHECK: $d0 = COPY [[ASHR]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $d0
+    %1:_(<2 x s32>) = COPY $d1
+    %2:_(<2 x s32>) = G_ASHR %0, %1
+    $d0 = COPY %2
+
+...
+---
+name: test_ashr_v4i32
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: test_ashr_v4i32
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+    ; CHECK: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[COPY]], [[COPY1]](<4 x s32>)
+    ; CHECK: $q0 = COPY [[ASHR]](<4 x s32>)
+    %0:_(<4 x s32>) = COPY $q0
+    %1:_(<4 x s32>) = COPY $q1
+    %2:_(<4 x s32>) = G_ASHR %0, %1
+    $q0 = COPY %2
+
+...
Index: llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -105,10 +105,10 @@
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder({G_LSHR, G_ASHR})
-    .legalFor({{s32, s32}, {s64, s64}})
-    .clampScalar(1, s32, s64)
-    .clampScalar(0, s32, s64)
-    .minScalarSameAs(1, 0);
+      .legalFor({{s32, s32}, {s64, s64}, {v2s32, v2s32}, {v4s32, v4s32}})
+      .clampScalar(1, s32, s64)
+      .clampScalar(0, s32, s64)
+      .minScalarSameAs(1, 0);
 
   getActionDefinitionsBuilder({G_SREM, G_UREM})
       .lowerFor({s1, s8, s16, s32, s64});
@@ -273,6 +273,9 @@
   getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
       .legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
 
+  getActionDefinitionsBuilder(G_TRUNC).legalIf(
+      [=](const LegalityQuery &Query) { return true; });
+
   // FP conversions
   getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
       {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}});


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