[PATCH] D59990: AMDGPU. Divergence driven ISel. Assign register class for cross block values according to the divergence.

[Alexander via Phabricator via llvm-commits]

alex-t marked an inline comment as done.
alex-t added inline comments.


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Comment at: include/llvm/CodeGen/TargetRegisterInfo.h:524-526
+  virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
+    return false;
+  }
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nhaehnle wrote:
> This function is problematic because we can't actually tell for a given register class whether the underlying value is divergent or not. Specifically, 64-bit SGPRs can be either uniform or divergent depending on whether it's the lowering of an i1 or an i64.
> 
This is not about the underlying value at all. 
This is a way to ask the target does it consider given register class as uniform or divergent.
In other words:  we cannot expose the concrete register class properties to the common code.
>From the other hand, the instruction description structure is common and it maps operand to register class.
While emitting the instruction we want to consult the target if the given operand required to be assigned the divergent (aka VGPR) register. This is not because of the value divergence but because the selected instruction.


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  https://reviews.llvm.org/D59990/new/

https://reviews.llvm.org/D59990