[PATCH] D60402: [PowerPC] Collapse RLDICL/RLDICR into RLDIC when possible

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, stefanp, jsji.
Herald added a subscriber: kbarton.
Herald added a project: LLVM.

Generally speaking, we lower to an optimal rotate sequence for nodes visible in the SDAG. However, there are instances where the two rotates are not visible at ISEL time - most notably those in a very common sequence when lowering `switch` statements to jump tables.
A common situation is a `switch` on a 32-bit integer. This value has to have the upper 32 bits cleared and because jump table offsets are word offsets, the value needs to be shifted left by 2 bits. We currently emit the clear and the left shift as two separate instructions, but this is not needed as we can lower it to a single `RLDIC`.
This patch just cleans that up.


Repository:
  rL LLVM

https://reviews.llvm.org/D60402

Files:
  lib/Target/PowerPC/PPCMIPeephole.cpp
  test/CodeGen/PowerPC/collapse-rotates.mir
  test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll

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