[PATCH] D60066: [llvm-exegesis][X86] Randomize CMOVcc/SETcc OPERAND_COND_CODE CondCodes

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL357898: [llvm-exegesis][X86] Randomize CMOVcc/SETcc OPERAND_COND_CODE CondCodes (authored by lebedevri, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D60066?vs=193082&id=194110#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60066/new/

https://reviews.llvm.org/D60066

Files:
  llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s
  llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp
  llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h
  llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp


Index: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
===================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
+++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -8,6 +8,7 @@
 #include "../Target.h"
 
 #include "../Latency.h"
+#include "../SnippetGenerator.h"
 #include "../Uops.h"
 #include "MCTargetDesc/X86BaseInfo.h"
 #include "MCTargetDesc/X86MCTargetDesc.h"
@@ -498,8 +499,8 @@
   const Operand &Op = Instr.getPrimaryOperand(Var);
   switch (Op.getExplicitOperandInfo().OperandType) {
   case llvm::X86::OperandType::OPERAND_COND_CODE:
-    // FIXME: explore all CC variants.
-    AssignedValue = llvm::MCOperand::createImm(1);
+    AssignedValue = llvm::MCOperand::createImm(
+        randomIndex(llvm::X86::CondCode::LAST_VALID_COND));
     break;
   default:
     break;
Index: llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h
===================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h
+++ llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h
@@ -77,6 +77,9 @@
 // unit tests.
 std::mt19937 &randomGenerator();
 
+// Picks a random unsigned integer from 0 to Max (inclusive).
+size_t randomIndex(size_t Max);
+
 // Picks a random bit among the bits set in Vector and returns its index.
 // Precondition: Vector must have at least one bit set.
 size_t randomBit(const llvm::BitVector &Vector);
Index: llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp
===================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -146,15 +146,16 @@
   return RandomGenerator;
 }
 
-static size_t randomIndex(size_t Size) {
-  assert(Size > 0);
-  std::uniform_int_distribution<> Distribution(0, Size - 1);
+size_t randomIndex(size_t Max) {
+  std::uniform_int_distribution<> Distribution(0, Max);
   return Distribution(randomGenerator());
 }
 
 template <typename C>
 static auto randomElement(const C &Container) -> decltype(Container[0]) {
-  return Container[randomIndex(Container.size())];
+  assert(!Container.empty() &&
+         "Can't pick a random element from an empty container)");
+  return Container[randomIndex(Container.size() - 1)];
 }
 
 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
@@ -176,7 +177,7 @@
 size_t randomBit(const llvm::BitVector &Vector) {
   assert(Vector.any());
   auto Itr = Vector.set_bits_begin();
-  for (size_t I = randomIndex(Vector.count()); I != 0; --I)
+  for (size_t I = randomIndex(Vector.count() - 1); I != 0; --I)
     ++Itr;
   return *Itr;
 }
Index: llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s
===================================================================
--- llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s
+++ llvm/trunk/test/tools/llvm-exegesis/X86/latency-CMOV32rr.s
@@ -4,6 +4,6 @@
 CHECK-NEXT: mode: latency
 CHECK-NEXT: key:
 CHECK-NEXT:   instructions:
-CHECK-NEXT:     CMOV32rr
+CHECK-NEXT:     'CMOV32rr {{.*}} i_0x{{[0-9a-f]}}'
 CHECK-NEXT: config: ''
 CHECK-LAST: ...


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