[PATCH] D60358: [TargetLowering][X86][AArch64] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

If the upper bits of the SHL result aren't used, we might be able to use a narrower shift. For example, on X86 this can turn a 64-bit into 32-bit enabling a smaller encoding.

The AArch64 change prevents a regression on one of the test cases in tbz-tbnz.ll where a 64-bit TBNZ is being fed by an any_ext and a 32-bit shl after this change.

One of the test cases for X86 regressed because we no longer form an LEA, but I think we can fix that will a little effort.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60358

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/X86/narrow-shl-cst.ll
  llvm/test/CodeGen/X86/zext-logicop-shift-load.ll


Index: llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
===================================================================
--- llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
+++ llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
@@ -5,8 +5,8 @@
 define i64 @test1(i8* %data) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl (%rdi), %eax
-; CHECK-NEXT:    shlq $2, %rax
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    shll $2, %eax
 ; CHECK-NEXT:    andl $60, %eax
 ; CHECK-NEXT:    retq
 entry:
@@ -20,9 +20,10 @@
 define i8* @test2(i8* %data) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl (%rdi), %eax
-; CHECK-NEXT:    andl $15, %eax
-; CHECK-NEXT:    leaq (%rdi,%rax,4), %rax
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    shll $2, %eax
+; CHECK-NEXT:    andl $60, %eax
+; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %bf.load = load i8, i8* %data, align 4
Index: llvm/test/CodeGen/X86/narrow-shl-cst.ll
===================================================================
--- llvm/test/CodeGen/X86/narrow-shl-cst.ll
+++ llvm/test/CodeGen/X86/narrow-shl-cst.ll
@@ -152,9 +152,8 @@
 define i64 @test13(i64 %x, i64* %y) nounwind {
 ; CHECK-LABEL: test13:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    andl $127, %eax
-; CHECK-NEXT:    addq %rax, %rax
+; CHECK-NEXT:    addl %edi, %edi
+; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    movq %rax, (%rsi)
 ; CHECK-NEXT:    retq
   %and = shl i64 %x, 1
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11038,6 +11038,12 @@
     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
   }
 
+  // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
+  if (Op->getOpcode() == ISD::ANY_EXTEND &&
+      Bit < Op->getOperand(0).getValueSizeInBits()) {
+    return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
+  }
+
   if (Op->getNumOperands() != 2)
     return Op;
 
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -922,6 +922,12 @@
                                Known, TLO, Depth + 1))
         return true;
 
+      // Try shrinking the operation as long as the shift amount will still be
+      // in range.
+      if ((ShAmt < DemandedBits.getActiveBits()) &&
+          ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
+        return true;
+
       // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
       // are not demanded. This will likely allow the anyext to be folded away.
       if (Op0.getOpcode() == ISD::ANY_EXTEND) {


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