[llvm] r357802 - [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 5 12:28:09 PDT 2019
Author: ctopper
Date: Fri Apr 5 12:28:09 2019
New Revision: 357802
URL: http://llvm.org/viewvc/llvm-project?rev=357802&view=rev
Log:
[X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.
Summary:
This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.
Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.
Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon
Reviewed By: RKSimon
Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60228
Modified:
llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
llvm/trunk/lib/Target/X86/X86CondBrFolding.cpp
llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrControl.td
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.h
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
llvm/trunk/lib/Target/X86/X86MacroFusion.cpp
llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp
llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir
llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
llvm/trunk/test/CodeGen/MIR/X86/branch-folder-with-label.mir
llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir
llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir
llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir
llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir
llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir
llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir
llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir
llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir
llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir
llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir
llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir
llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-brcond.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir
llvm/trunk/test/CodeGen/X86/PR37310.mir
llvm/trunk/test/CodeGen/X86/block-placement.mir
llvm/trunk/test/CodeGen/X86/branchfolding-undef.mir
llvm/trunk/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir
llvm/trunk/test/CodeGen/X86/cfi-inserter-noreturnblock.mir
llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir
llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir
llvm/trunk/test/CodeGen/X86/cmovcmov.ll
llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir
llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir
llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll
llvm/trunk/test/CodeGen/X86/domain-reassignment.mir
llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir
llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir
llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
llvm/trunk/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
llvm/trunk/test/CodeGen/X86/invalid-liveness.mir
llvm/trunk/test/CodeGen/X86/late-remat-update-2.mir
llvm/trunk/test/CodeGen/X86/late-remat-update.mir
llvm/trunk/test/CodeGen/X86/leaFixup32.mir
llvm/trunk/test/CodeGen/X86/leaFixup64.mir
llvm/trunk/test/CodeGen/X86/limit-split-cost.mir
llvm/trunk/test/CodeGen/X86/machine-region-info.mir
llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir
llvm/trunk/test/CodeGen/X86/opt_phis2.mir
llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir
llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir
llvm/trunk/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
llvm/trunk/test/CodeGen/X86/pr27681.mir
llvm/trunk/test/CodeGen/X86/pr38952.mir
llvm/trunk/test/CodeGen/X86/pre-coalesce.mir
llvm/trunk/test/CodeGen/X86/regalloc-copy-hints.mir
llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir
llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir
llvm/trunk/test/CodeGen/X86/switch-lower-peel-top-case.ll
llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir
llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll
llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir
llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll
llvm/trunk/test/CodeGen/X86/test_x86condbr_globaladdr.mir
llvm/trunk/test/CodeGen/X86/undef-eflags.mir
llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll
llvm/trunk/test/CodeGen/X86/update-terminator.mir
llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll
llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir
llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
llvm/trunk/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
llvm/trunk/test/DebugInfo/X86/debug-loc-asan.mir
llvm/trunk/test/DebugInfo/X86/debug-loc-offset.mir
llvm/trunk/test/DebugInfo/X86/pr19307.mir
llvm/trunk/test/MachineVerifier/verifier-phi-fail0.mir
llvm/trunk/test/MachineVerifier/verifier-phi.mir
llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
llvm/trunk/utils/TableGen/X86RecognizableInstr.h
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Fri Apr 5 12:28:09 2019
@@ -782,7 +782,7 @@ static bool translateOperand(MCInst &mcI
translateRegister(mcInst, insn.opcodeRegister);
return false;
case ENCODING_CC:
- mcInst.addOperand(MCOperand::createImm(insn.immediates[0]));
+ mcInst.addOperand(MCOperand::createImm(insn.immediates[1]));
return false;
case ENCODING_FP:
translateFPRegister(mcInst, insn.modRM & 7);
Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Fri Apr 5 12:28:09 2019
@@ -1847,7 +1847,7 @@ static int readOperands(struct InternalI
return -1;
break;
case ENCODING_CC:
- insn->immediates[0] = insn->opcode & 0xf;
+ insn->immediates[1] = insn->opcode & 0xf;
break;
case ENCODING_FP:
break;
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Fri Apr 5 12:28:09 2019
@@ -136,40 +136,10 @@ static unsigned getRelaxedOpcodeBranch(c
switch (Op) {
default:
return Op;
- case X86::JAE_1:
- return (is16BitMode) ? X86::JAE_2 : X86::JAE_4;
- case X86::JA_1:
- return (is16BitMode) ? X86::JA_2 : X86::JA_4;
- case X86::JBE_1:
- return (is16BitMode) ? X86::JBE_2 : X86::JBE_4;
- case X86::JB_1:
- return (is16BitMode) ? X86::JB_2 : X86::JB_4;
- case X86::JE_1:
- return (is16BitMode) ? X86::JE_2 : X86::JE_4;
- case X86::JGE_1:
- return (is16BitMode) ? X86::JGE_2 : X86::JGE_4;
- case X86::JG_1:
- return (is16BitMode) ? X86::JG_2 : X86::JG_4;
- case X86::JLE_1:
- return (is16BitMode) ? X86::JLE_2 : X86::JLE_4;
- case X86::JL_1:
- return (is16BitMode) ? X86::JL_2 : X86::JL_4;
+ case X86::JCC_1:
+ return (is16BitMode) ? X86::JCC_2 : X86::JCC_4;
case X86::JMP_1:
return (is16BitMode) ? X86::JMP_2 : X86::JMP_4;
- case X86::JNE_1:
- return (is16BitMode) ? X86::JNE_2 : X86::JNE_4;
- case X86::JNO_1:
- return (is16BitMode) ? X86::JNO_2 : X86::JNO_4;
- case X86::JNP_1:
- return (is16BitMode) ? X86::JNP_2 : X86::JNP_4;
- case X86::JNS_1:
- return (is16BitMode) ? X86::JNS_2 : X86::JNS_4;
- case X86::JO_1:
- return (is16BitMode) ? X86::JO_2 : X86::JO_4;
- case X86::JP_1:
- return (is16BitMode) ? X86::JP_2 : X86::JP_4;
- case X86::JS_1:
- return (is16BitMode) ? X86::JS_2 : X86::JS_4;
}
}
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Fri Apr 5 12:28:09 2019
@@ -321,6 +321,10 @@ namespace X86II {
/// manual, this operand is described as pntr16:32 and pntr16:16
RawFrmImm16 = 8,
+ /// AddCCFrm - This form is used for Jcc that encode the condition code
+ /// in the lower 4 bits of the opcode.
+ AddCCFrm = 9,
+
/// MRM[0-7][rm] - These forms are used to represent instructions that use
/// a Mod/RM byte, and use the middle field to hold extended opcode
/// information. In the intel manual these are represented as /0, /1, ...
@@ -769,6 +773,7 @@ namespace X86II {
case X86II::RawFrmSrc:
case X86II::RawFrmDst:
case X86II::RawFrmDstSrc:
+ case X86II::AddCCFrm:
return -1;
case X86II::MRMDestMem:
return 0;
Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Fri Apr 5 12:28:09 2019
@@ -1273,6 +1273,8 @@ encodeInstruction(const MCInst &MI, raw_
if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
BaseOpcode = 0x0F; // Weird 3DNow! encoding.
+ unsigned OpcodeOffset = 0;
+
uint64_t Form = TSFlags & X86II::FormMask;
switch (Form) {
default: errs() << "FORM: " << Form << "\n";
@@ -1319,8 +1321,14 @@ encodeInstruction(const MCInst &MI, raw_
EmitByte(BaseOpcode, CurByte, OS);
break;
}
- case X86II::RawFrm: {
- EmitByte(BaseOpcode, CurByte, OS);
+ case X86II::AddCCFrm: {
+ // This will be added to the opcode in the fallthrough.
+ OpcodeOffset = MI.getOperand(NumOps - 1).getImm();
+ assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
+ --NumOps; // Drop the operand from the end.
+ LLVM_FALLTHROUGH;
+ case X86II::RawFrm:
+ EmitByte(BaseOpcode + OpcodeOffset, CurByte, OS);
if (!is64BitMode(STI) || !isPCRel32Branch(MI))
break;
Modified: llvm/trunk/lib/Target/X86/X86CmovConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CmovConversion.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CmovConversion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CmovConversion.cpp Fri Apr 5 12:28:09 2019
@@ -689,7 +689,7 @@ void X86CmovConverterPass::convertCmovIn
MBB->addSuccessor(SinkMBB);
// Create the conditional branch instruction.
- BuildMI(MBB, DL, TII->get(X86::GetCondBranchFromCond(CC))).addMBB(SinkMBB);
+ BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
// Add the sink block to the false block successors.
FalseMBB->addSuccessor(SinkMBB);
Modified: llvm/trunk/lib/Target/X86/X86CondBrFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CondBrFolding.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CondBrFolding.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CondBrFolding.cpp Fri Apr 5 12:28:09 2019
@@ -225,10 +225,9 @@ void X86CondBrFolding::replaceBrDest(Mac
MachineInstr *BrMI;
if (MBBInfo->TBB == OrigDest) {
BrMI = MBBInfo->BrInstr;
- unsigned JNCC = GetCondBranchFromCond(MBBInfo->BranchCode);
MachineInstrBuilder MIB =
- BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(JNCC))
- .addMBB(NewDest);
+ BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1))
+ .addMBB(NewDest).addImm(MBBInfo->BranchCode);
MBBInfo->TBB = NewDest;
MBBInfo->BrInstr = MIB.getInstr();
} else { // Should be the unconditional jump stmt.
@@ -254,8 +253,8 @@ void X86CondBrFolding::fixupModifiedCond
MachineInstr *BrMI = MBBInfo->BrInstr;
X86::CondCode CC = MBBInfo->BranchCode;
MachineInstrBuilder MIB = BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI),
- TII->get(GetCondBranchFromCond(CC)))
- .addMBB(MBBInfo->TBB);
+ TII->get(X86::JCC_1))
+ .addMBB(MBBInfo->TBB).addImm(CC);
BrMI->eraseFromParent();
MBBInfo->BrInstr = MIB.getInstr();
@@ -323,8 +322,8 @@ void X86CondBrFolding::optimizeCondBr(
llvm_unreachable("unexpected condtional code.");
}
BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
- TII->get(GetCondBranchFromCond(NewCC)))
- .addMBB(RootMBBInfo->FBB);
+ TII->get(X86::JCC_1))
+ .addMBB(RootMBBInfo->FBB).addImm(NewCC);
// RootMBB: Jump to TargetMBB
BuildMI(*RootMBB, UncondBrI, RootMBB->findDebugLoc(UncondBrI),
@@ -512,7 +511,7 @@ X86CondBrFolding::analyzeMBB(MachineBasi
if (I->isBranch()) {
if (TBB)
return nullptr;
- CC = X86::getCondFromBranchOpc(I->getOpcode());
+ CC = X86::getCondFromBranch(*I);
switch (CC) {
default:
return nullptr;
Modified: llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp Fri Apr 5 12:28:09 2019
@@ -100,8 +100,8 @@ void X86ExpandPseudo::ExpandICallBranchF
return NewMBB;
};
- auto EmitCondJump = [&](unsigned Opcode, MachineBasicBlock *ThenMBB) {
- BuildMI(*MBB, MBBI, DL, TII->get(Opcode)).addMBB(ThenMBB);
+ auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
+ BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
auto *ElseMBB = CreateMBB();
MF->insert(InsPt, ElseMBB);
@@ -109,10 +109,10 @@ void X86ExpandPseudo::ExpandICallBranchF
MBBI = MBB->end();
};
- auto EmitCondJumpTarget = [&](unsigned Opcode, unsigned Target) {
+ auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
auto *ThenMBB = CreateMBB();
TargetMBBs.push_back({ThenMBB, Target});
- EmitCondJump(Opcode, ThenMBB);
+ EmitCondJump(CC, ThenMBB);
};
auto EmitTailCall = [&](unsigned Target) {
@@ -129,23 +129,23 @@ void X86ExpandPseudo::ExpandICallBranchF
if (NumTargets == 2) {
CmpTarget(FirstTarget + 1);
- EmitCondJumpTarget(X86::JB_1, FirstTarget);
+ EmitCondJumpTarget(X86::COND_B, FirstTarget);
EmitTailCall(FirstTarget + 1);
return;
}
if (NumTargets < 6) {
CmpTarget(FirstTarget + 1);
- EmitCondJumpTarget(X86::JB_1, FirstTarget);
- EmitCondJumpTarget(X86::JE_1, FirstTarget + 1);
+ EmitCondJumpTarget(X86::COND_B, FirstTarget);
+ EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
return;
}
auto *ThenMBB = CreateMBB();
CmpTarget(FirstTarget + (NumTargets / 2));
- EmitCondJump(X86::JB_1, ThenMBB);
- EmitCondJumpTarget(X86::JE_1, FirstTarget + (NumTargets / 2));
+ EmitCondJump(X86::COND_B, ThenMBB);
+ EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
NumTargets - (NumTargets / 2) - 1);
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Apr 5 12:28:09 2019
@@ -1690,11 +1690,9 @@ bool X86FastISel::X86SelectBranch(const
}
bool SwapArgs;
- unsigned BranchOpc;
std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate);
assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
- BranchOpc = X86::GetCondBranchFromCond(CC);
if (SwapArgs)
std::swap(CmpLHS, CmpRHS);
@@ -1702,14 +1700,14 @@ bool X86FastISel::X86SelectBranch(const
if (!X86FastEmitCompare(CmpLHS, CmpRHS, VT, CI->getDebugLoc()))
return false;
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
- .addMBB(TrueMBB);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+ .addMBB(TrueMBB).addImm(CC);
// X86 requires a second branch to handle UNE (and OEQ, which is mapped
// to UNE above).
if (NeedExtraBranch) {
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_1))
- .addMBB(TrueMBB);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+ .addMBB(TrueMBB).addImm(X86::COND_P);
}
finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
@@ -1736,14 +1734,14 @@ bool X86FastISel::X86SelectBranch(const
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
.addReg(OpReg).addImm(1);
- unsigned JmpOpc = X86::JNE_1;
+ unsigned JmpCond = X86::COND_NE;
if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
std::swap(TrueMBB, FalseMBB);
- JmpOpc = X86::JE_1;
+ JmpCond = X86::COND_E;
}
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(JmpOpc))
- .addMBB(TrueMBB);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+ .addMBB(TrueMBB).addImm(JmpCond);
finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
return true;
@@ -1756,10 +1754,8 @@ bool X86FastISel::X86SelectBranch(const
if (TmpReg == 0)
return false;
- unsigned BranchOpc = X86::GetCondBranchFromCond(CC);
-
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
- .addMBB(TrueMBB);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+ .addMBB(TrueMBB).addImm(CC);
finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
return true;
}
@@ -1783,8 +1779,8 @@ bool X86FastISel::X86SelectBranch(const
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
.addReg(OpReg)
.addImm(1);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_1))
- .addMBB(TrueMBB);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
+ .addMBB(TrueMBB).addImm(X86::COND_NE);
finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
return true;
}
Modified: llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp Fri Apr 5 12:28:09 2019
@@ -251,13 +251,13 @@ static MachineBasicBlock &splitBlock(Mac
"Split instruction must be in the split block!");
assert(SplitI.isBranch() &&
"Only designed to split a tail of branch instructions!");
- assert(X86::getCondFromBranchOpc(SplitI.getOpcode()) != X86::COND_INVALID &&
+ assert(X86::getCondFromBranch(SplitI) != X86::COND_INVALID &&
"Must split on an actual jCC instruction!");
// Dig out the previous instruction to the split point.
MachineInstr &PrevI = *std::prev(SplitI.getIterator());
assert(PrevI.isBranch() && "Must split after a branch!");
- assert(X86::getCondFromBranchOpc(PrevI.getOpcode()) != X86::COND_INVALID &&
+ assert(X86::getCondFromBranch(PrevI) != X86::COND_INVALID &&
"Must split after an actual jCC instruction!");
assert(!std::prev(PrevI.getIterator())->isTerminator() &&
"Must only have this one terminator prior to the split!");
@@ -587,13 +587,13 @@ bool X86FlagsCopyLoweringPass::runOnMach
// branch folding or black placement. As a consequence, we get to deal
// with the simpler formulation of conditional branches followed by tail
// calls.
- if (X86::getCondFromBranchOpc(MI.getOpcode()) != X86::COND_INVALID) {
+ if (X86::getCondFromBranch(MI) != X86::COND_INVALID) {
auto JmpIt = MI.getIterator();
do {
JmpIs.push_back(&*JmpIt);
++JmpIt;
} while (JmpIt != UseMBB.instr_end() &&
- X86::getCondFromBranchOpc(JmpIt->getOpcode()) !=
+ X86::getCondFromBranch(*JmpIt) !=
X86::COND_INVALID);
break;
}
@@ -863,7 +863,7 @@ void X86FlagsCopyLoweringPass::rewriteCo
MachineBasicBlock &TestMBB, MachineBasicBlock::iterator TestPos,
DebugLoc TestLoc, MachineInstr &JmpI, CondRegArray &CondRegs) {
// First get the register containing this specific condition.
- X86::CondCode Cond = X86::getCondFromBranchOpc(JmpI.getOpcode());
+ X86::CondCode Cond = X86::getCondFromBranch(JmpI);
unsigned CondReg;
bool Inverted;
std::tie(CondReg, Inverted) =
@@ -876,10 +876,8 @@ void X86FlagsCopyLoweringPass::rewriteCo
// Rewrite the jump to use the !ZF flag from the test, and kill its use of
// flags afterward.
- JmpI.setDesc(TII->get(
- X86::GetCondBranchFromCond(Inverted ? X86::COND_E : X86::COND_NE)));
- const int ImplicitEFLAGSOpIdx = 1;
- JmpI.getOperand(ImplicitEFLAGSOpIdx).setIsKill(true);
+ JmpI.getOperand(1).setImm(Inverted ? X86::COND_E : X86::COND_NE);
+ JmpI.findRegisterUseOperand(X86::EFLAGS)->setIsKill(true);
LLVM_DEBUG(dbgs() << " fixed jCC: "; JmpI.dump());
}
Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Fri Apr 5 12:28:09 2019
@@ -673,7 +673,7 @@ void X86FrameLowering::emitStackProbeInl
.addReg(X86::GS);
BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
// Jump if the desired stack pointer is at or above the stack limit.
- BuildMI(&MBB, DL, TII.get(X86::JAE_1)).addMBB(ContinueMBB);
+ BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
// Add code to roundMBB to round the final stack pointer to a page boundary.
RoundMBB->addLiveIn(FinalReg);
@@ -710,7 +710,7 @@ void X86FrameLowering::emitStackProbeInl
BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
.addReg(RoundedReg)
.addReg(ProbeReg);
- BuildMI(LoopMBB, DL, TII.get(X86::JNE_1)).addMBB(LoopMBB);
+ BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
@@ -2416,7 +2416,7 @@ void X86FrameLowering::adjustForSegmente
// This jump is taken if SP >= (Stacklet Limit + Stack Space required).
// It jumps to normal execution of the function body.
- BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
+ BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
// On 32 bit we first push the arguments size and then the frame size. On 64
// bit, we pass the stack frame size in r10 and the argument size in r11.
@@ -2646,7 +2646,7 @@ void X86FrameLowering::adjustForHiPEProl
// SPLimitOffset is in a fixed heap location (pointed by BP).
addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
.addReg(ScratchReg), PReg, false, SPLimitOffset);
- BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
+ BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
// Create new MBB for IncStack:
BuildMI(incStackMBB, DL, TII.get(CALLop)).
@@ -2655,7 +2655,7 @@ void X86FrameLowering::adjustForHiPEProl
SPReg, false, -MaxStack);
addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
.addReg(ScratchReg), PReg, false, SPLimitOffset);
- BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
+ BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Apr 5 12:28:09 2019
@@ -2324,21 +2324,19 @@ bool X86DAGToDAGISel::isSExtAbsoluteSymb
static X86::CondCode getCondFromNode(SDNode *N) {
assert(N->isMachineOpcode() && "Unexpected node");
X86::CondCode CC = X86::COND_INVALID;
- if (CC == X86::COND_INVALID)
- CC = X86::getCondFromBranchOpc(N->getMachineOpcode());
- if (CC == X86::COND_INVALID) {
- unsigned Opc = N->getMachineOpcode();
- if (Opc == X86::SETCCr)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(0));
- else if (Opc == X86::SETCCm)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(5));
- else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
- Opc == X86::CMOV64rr)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(2));
- else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
- Opc == X86::CMOV64rm)
- CC = static_cast<X86::CondCode>(N->getConstantOperandVal(6));
- }
+ unsigned Opc = N->getMachineOpcode();
+ if (Opc == X86::JCC_1)
+ CC = static_cast<X86::CondCode>(N->getConstantOperandVal(1));
+ else if (Opc == X86::SETCCr)
+ CC = static_cast<X86::CondCode>(N->getConstantOperandVal(0));
+ else if (Opc == X86::SETCCm)
+ CC = static_cast<X86::CondCode>(N->getConstantOperandVal(5));
+ else if (Opc == X86::CMOV16rr || Opc == X86::CMOV32rr ||
+ Opc == X86::CMOV64rr)
+ CC = static_cast<X86::CondCode>(N->getConstantOperandVal(2));
+ else if (Opc == X86::CMOV16rm || Opc == X86::CMOV32rm ||
+ Opc == X86::CMOV64rm)
+ CC = static_cast<X86::CondCode>(N->getConstantOperandVal(6));
return CC;
}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Apr 5 12:28:09 2019
@@ -28422,8 +28422,8 @@ X86TargetLowering::EmitVAARG64WithCustom
// Branch to "overflowMBB" if offset >= max
// Fall through to "offsetMBB" otherwise
- BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
- .addMBB(overflowMBB);
+ BuildMI(thisMBB, DL, TII->get(X86::JCC_1))
+ .addMBB(overflowMBB).addImm(X86::COND_AE);
}
// In offsetMBB, emit code to use the reg_save_area.
@@ -28580,7 +28580,7 @@ MachineBasicBlock *X86TargetLowering::Em
if (!Subtarget.isCallingConvWin64(F->getFunction().getCallingConv())) {
// If %al is 0, branch around the XMM save block.
BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
- BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
+ BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
MBB->addSuccessor(EndMBB);
}
@@ -28860,13 +28860,11 @@ X86TargetLowering::EmitLoweredCascadedSe
// Create the conditional branch instructions.
X86::CondCode FirstCC = X86::CondCode(FirstCMOV.getOperand(3).getImm());
- unsigned Opc = X86::GetCondBranchFromCond(FirstCC);
- BuildMI(ThisMBB, DL, TII->get(Opc)).addMBB(SinkMBB);
+ BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
X86::CondCode SecondCC =
X86::CondCode(SecondCascadedCMOV.getOperand(3).getImm());
- unsigned Opc2 = X86::GetCondBranchFromCond(SecondCC);
- BuildMI(FirstInsertedMBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
+ BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
// SinkMBB:
// %Result = phi [ %FalseValue, SecondInsertedMBB ], [ %TrueValue, ThisMBB ]
@@ -29022,8 +29020,7 @@ X86TargetLowering::EmitLoweredSelect(Mac
FalseMBB->addSuccessor(SinkMBB);
// Create the conditional branch instruction.
- unsigned Opc = X86::GetCondBranchFromCond(CC);
- BuildMI(ThisMBB, DL, TII->get(Opc)).addMBB(SinkMBB);
+ BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
// SinkMBB:
// %Result = phi [ %FalseValue, FalseMBB ], [ %TrueValue, ThisMBB ]
@@ -29152,7 +29149,7 @@ X86TargetLowering::EmitLoweredSegAlloca(
BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
.addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
.addReg(SPLimitVReg);
- BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
+ BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
// bumpMBB simply decreases the stack pointer, since we know the current
// stacklet has enough space.
@@ -29779,7 +29776,7 @@ X86TargetLowering::emitLongJmpShadowStac
BuildMI(checkSspMBB, DL, TII->get(TestRROpc))
.addReg(SSPCopyReg)
.addReg(SSPCopyReg);
- BuildMI(checkSspMBB, DL, TII->get(X86::JE_1)).addMBB(sinkMBB);
+ BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
checkSspMBB->addSuccessor(sinkMBB);
checkSspMBB->addSuccessor(fallMBB);
@@ -29809,7 +29806,7 @@ X86TargetLowering::emitLongJmpShadowStac
.addReg(SSPCopyReg);
// Jump to sink in case PrevSSPReg <= SSPCopyReg.
- BuildMI(fallMBB, DL, TII->get(X86::JBE_1)).addMBB(sinkMBB);
+ BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
fallMBB->addSuccessor(sinkMBB);
fallMBB->addSuccessor(fixShadowMBB);
@@ -29832,7 +29829,7 @@ X86TargetLowering::emitLongJmpShadowStac
.addImm(8);
// Jump if the result of the shift is zero.
- BuildMI(fixShadowMBB, DL, TII->get(X86::JE_1)).addMBB(sinkMBB);
+ BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
fixShadowMBB->addSuccessor(sinkMBB);
fixShadowMBB->addSuccessor(fixShadowLoopPrepareMBB);
@@ -29867,7 +29864,7 @@ X86TargetLowering::emitLongJmpShadowStac
BuildMI(fixShadowLoopMBB, DL, TII->get(DecROpc), DecReg).addReg(CounterReg);
// Jump if the counter is not zero yet.
- BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JNE_1)).addMBB(fixShadowLoopMBB);
+ BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
fixShadowLoopMBB->addSuccessor(sinkMBB);
fixShadowLoopMBB->addSuccessor(fixShadowLoopMBB);
@@ -30113,7 +30110,7 @@ X86TargetLowering::EmitSjLjDispatchBlock
BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
.addReg(IReg)
.addImm(LPadList.size());
- BuildMI(DispatchBB, DL, TII->get(X86::JAE_1)).addMBB(TrapBB);
+ BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
if (Subtarget.is64Bit()) {
unsigned BReg = MRI->createVirtualRegister(&X86::GR64RegClass);
Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrControl.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrControl.td Fri Apr 5 12:28:09 2019
@@ -70,35 +70,40 @@ let isBarrier = 1, isBranch = 1, isTermi
}
// Conditional Branches.
-let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
- multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
- def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
- [(X86brcond bb:$dst, Cond, EFLAGS)]>;
- let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
- def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm,
- []>, OpSize16, TB;
- def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm,
- []>, TB, OpSize32;
- }
+let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
+ isCodeGenOnly = 1, ForceDisassemble = 1 in {
+ def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs),
+ (ins brtarget8:$dst, ccode:$cond),
+ "j${cond}\t$dst",
+ [(X86brcond bb:$dst, imm:$cond, EFLAGS)]>;
+ let hasSideEffects = 0 in {
+ def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs),
+ (ins brtarget16:$dst, ccode:$cond),
+ "j${cond}\t$dst",
+ []>, OpSize16, TB;
+ def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs),
+ (ins brtarget32:$dst, ccode:$cond),
+ "j${cond}\t$dst",
+ []>, TB, OpSize32;
}
}
-defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
-defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
-defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
-defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
-defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
-defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
-defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
-defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
-defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
-defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
-defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
-defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
-defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
-defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
-defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
-defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
+def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>;
+def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>;
+def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>;
+def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>;
+def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>;
+def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>;
+def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>;
+def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>;
+def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>;
+def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>;
+def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>;
+def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>;
+def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>;
+def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>;
+def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>;
+def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>;
// jcx/jecx/jrcx instructions.
let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Fri Apr 5 12:28:09 2019
@@ -26,6 +26,7 @@ def RawFrmDst : Format<5>;
def RawFrmDstSrc : Format<6>;
def RawFrmImm8 : Format<7>;
def RawFrmImm16 : Format<8>;
+def AddCCFrm : Format<9>;
def MRMDestMem : Format<32>;
def MRMSrcMem : Format<33>;
def MRMSrcMem4VOp3 : Format<34>;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Apr 5 12:28:09 2019
@@ -1979,25 +1979,12 @@ bool X86InstrInfo::findCommutedOpIndices
return false;
}
-X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
- switch (BrOpc) {
+X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
default: return X86::COND_INVALID;
- case X86::JE_1: return X86::COND_E;
- case X86::JNE_1: return X86::COND_NE;
- case X86::JL_1: return X86::COND_L;
- case X86::JLE_1: return X86::COND_LE;
- case X86::JG_1: return X86::COND_G;
- case X86::JGE_1: return X86::COND_GE;
- case X86::JB_1: return X86::COND_B;
- case X86::JBE_1: return X86::COND_BE;
- case X86::JA_1: return X86::COND_A;
- case X86::JAE_1: return X86::COND_AE;
- case X86::JS_1: return X86::COND_S;
- case X86::JNS_1: return X86::COND_NS;
- case X86::JP_1: return X86::COND_P;
- case X86::JNP_1: return X86::COND_NP;
- case X86::JO_1: return X86::COND_O;
- case X86::JNO_1: return X86::COND_NO;
+ case X86::JCC_1:
+ return static_cast<X86::CondCode>(
+ MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
}
}
@@ -2022,28 +2009,6 @@ X86::CondCode X86::getCondFromCMov(const
}
}
-unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
- switch (CC) {
- default: llvm_unreachable("Illegal condition code!");
- case X86::COND_E: return X86::JE_1;
- case X86::COND_NE: return X86::JNE_1;
- case X86::COND_L: return X86::JL_1;
- case X86::COND_LE: return X86::JLE_1;
- case X86::COND_G: return X86::JG_1;
- case X86::COND_GE: return X86::JGE_1;
- case X86::COND_B: return X86::JB_1;
- case X86::COND_BE: return X86::JBE_1;
- case X86::COND_A: return X86::JA_1;
- case X86::COND_AE: return X86::JAE_1;
- case X86::COND_S: return X86::JS_1;
- case X86::COND_NS: return X86::JNS_1;
- case X86::COND_P: return X86::JP_1;
- case X86::COND_NP: return X86::JNP_1;
- case X86::COND_O: return X86::JO_1;
- case X86::COND_NO: return X86::JNO_1;
- }
-}
-
/// Return the inverse of the specified condition,
/// e.g. turning COND_E to COND_NE.
X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
@@ -2263,7 +2228,7 @@ void X86InstrInfo::replaceBranchWithTail
if (!I->isBranch())
assert(0 && "Can't find the branch to replace!");
- X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
+ X86::CondCode CC = X86::getCondFromBranch(*I);
assert(BranchCond.size() == 1);
if (CC != BranchCond[0].getImm())
continue;
@@ -2370,13 +2335,13 @@ bool X86InstrInfo::AnalyzeBranchImpl(
}
// Handle conditional branches.
- X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
+ X86::CondCode BranchCode = X86::getCondFromBranch(*I);
if (BranchCode == X86::COND_INVALID)
return true; // Can't handle indirect branch.
// In practice we should never have an undef eflags operand, if we do
// abort here as we are not prepared to preserve the flag.
- if (I->getOperand(1).isUndef())
+ if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
return true;
// Working from the bottom, handle the first conditional branch.
@@ -2402,11 +2367,11 @@ bool X86InstrInfo::AnalyzeBranchImpl(
// Which is a bit more efficient.
// We conditionally jump to the fall-through block.
BranchCode = GetOppositeBranchCondition(BranchCode);
- unsigned JNCC = GetCondBranchFromCond(BranchCode);
MachineBasicBlock::iterator OldInst = I;
- BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
- .addMBB(UnCondBrIter->getOperand(0).getMBB());
+ BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
+ .addMBB(UnCondBrIter->getOperand(0).getMBB())
+ .addImm(BranchCode);
BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
.addMBB(TargetBB);
@@ -2571,7 +2536,7 @@ unsigned X86InstrInfo::removeBranch(Mach
if (I->isDebugInstr())
continue;
if (I->getOpcode() != X86::JMP_1 &&
- X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
+ X86::getCondFromBranch(*I) == X86::COND_INVALID)
break;
// Remove the branch.
I->eraseFromParent();
@@ -2610,9 +2575,9 @@ unsigned X86InstrInfo::insertBranch(Mach
switch (CC) {
case X86::COND_NE_OR_P:
// Synthesize NE_OR_P with two branches.
- BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
++Count;
- BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
++Count;
break;
case X86::COND_E_AND_NP:
@@ -2623,14 +2588,13 @@ unsigned X86InstrInfo::insertBranch(Mach
"body is a fall-through.");
}
// Synthesize COND_E_AND_NP with two branches.
- BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
++Count;
- BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
++Count;
break;
default: {
- unsigned Opc = GetCondBranchFromCond(CC);
- BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
+ BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
++Count;
}
}
@@ -3541,7 +3505,7 @@ bool X86InstrInfo::optimizeCompareInstr(
if (IsCmpZero || IsSwapped) {
// We decode the condition code from opcode.
if (Instr.isBranch())
- OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
+ OldCC = X86::getCondFromBranch(Instr);
else {
OldCC = X86::getCondFromSETCC(Instr);
if (OldCC == X86::COND_INVALID)
@@ -3648,11 +3612,8 @@ bool X86InstrInfo::optimizeCompareInstr(
// Modify the condition code of instructions in OpsToUpdate.
for (auto &Op : OpsToUpdate) {
- if (Op.first->isBranch())
- Op.first->setDesc(get(GetCondBranchFromCond(Op.second)));
- else
- Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
- .setImm(Op.second);
+ Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
+ .setImm(Op.second);
}
return true;
}
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Apr 5 12:28:09 2019
@@ -35,9 +35,6 @@ enum AsmComments {
AC_EVEX_2_VEX = MachineInstr::TAsmComments
};
-// Turn condition code into conditional branch opcode.
-unsigned GetCondBranchFromCond(CondCode CC);
-
/// Return a pair of condition code for the given predicate and whether
/// the instruction operands should be swaped to match the condition code.
std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
@@ -48,13 +45,13 @@ unsigned getSETOpc(bool HasMemoryOperand
/// Return a cmov opcode for the given register size in bytes, and operand type.
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
-// Turn jCC opcode into condition code.
-CondCode getCondFromBranchOpc(unsigned Opc);
+// Turn jCC instruction into condition code.
+CondCode getCondFromBranch(const MachineInstr &MI);
-// Turn setCC opcode into condition code.
+// Turn setCC instruction into condition code.
CondCode getCondFromSETCC(const MachineInstr &MI);
-// Turn CMov opcode into condition code.
+// Turn CMov instruction into condition code.
CondCode getCondFromCMov(const MachineInstr &MI);
/// GetOppositeBranchCondition - Return the inverse of the specified cond,
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Fri Apr 5 12:28:09 2019
@@ -1418,8 +1418,8 @@ bool X86InstructionSelector::selectCondB
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
.addReg(CondReg)
.addImm(1);
- BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JNE_1))
- .addMBB(DestMBB);
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
+ .addMBB(DestMBB).addImm(X86::COND_NE);
constrainSelectedInstRegOperands(TestInst, TII, TRI, RBI);
Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Fri Apr 5 12:28:09 2019
@@ -550,11 +550,6 @@ void X86MCInstLower::Lower(const Machine
case X86::TAILJMPd64:
Opcode = X86::JMP_1;
goto SetTailJmpOpcode;
- case X86::TAILJMPd_CC:
- case X86::TAILJMPd64_CC:
- Opcode = X86::GetCondBranchFromCond(
- static_cast<X86::CondCode>(MI->getOperand(1).getImm()));
- goto SetTailJmpOpcode;
SetTailJmpOpcode:
MCOperand Saved = OutMI.getOperand(0);
@@ -564,6 +559,17 @@ void X86MCInstLower::Lower(const Machine
break;
}
+ case X86::TAILJMPd_CC:
+ case X86::TAILJMPd64_CC: {
+ MCOperand Saved = OutMI.getOperand(0);
+ MCOperand Saved2 = OutMI.getOperand(1);
+ OutMI = MCInst();
+ OutMI.setOpcode(X86::JCC_1);
+ OutMI.addOperand(Saved);
+ OutMI.addOperand(Saved2);
+ break;
+ }
+
case X86::DEC16r:
case X86::DEC32r:
case X86::INC16r:
Modified: llvm/trunk/lib/Target/X86/X86MacroFusion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MacroFusion.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MacroFusion.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MacroFusion.cpp Fri Apr 5 12:28:09 2019
@@ -145,27 +145,31 @@ static FirstInstrKind classifyFirst(cons
}
static JumpKind classifySecond(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
+ X86::CondCode CC = X86::getCondFromBranch(MI);
+ if (CC == X86::COND_INVALID)
+ return JumpKind::Invalid;
+
+ switch (CC) {
default:
return JumpKind::Invalid;
- case X86::JE_1:
- case X86::JNE_1:
- case X86::JL_1:
- case X86::JLE_1:
- case X86::JG_1:
- case X86::JGE_1:
+ case X86::COND_E:
+ case X86::COND_NE:
+ case X86::COND_L:
+ case X86::COND_LE:
+ case X86::COND_G:
+ case X86::COND_GE:
return JumpKind::ELG;
- case X86::JB_1:
- case X86::JBE_1:
- case X86::JA_1:
- case X86::JAE_1:
+ case X86::COND_B:
+ case X86::COND_BE:
+ case X86::COND_A:
+ case X86::COND_AE:
return JumpKind::AB;
- case X86::JS_1:
- case X86::JNS_1:
- case X86::JP_1:
- case X86::JNP_1:
- case X86::JO_1:
- case X86::JNO_1:
+ case X86::COND_S:
+ case X86::COND_NS:
+ case X86::COND_P:
+ case X86::COND_NP:
+ case X86::COND_O:
+ case X86::COND_NO:
return JumpKind::SPO;
}
}
Modified: llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp Fri Apr 5 12:28:09 2019
@@ -660,7 +660,7 @@ X86SpeculativeLoadHardeningPass::collect
// jmpq *%rax
// ```
// We still want to harden the edge to `L1`.
- if (X86::getCondFromBranchOpc(MI.getOpcode()) == X86::COND_INVALID) {
+ if (X86::getCondFromBranch(MI) == X86::COND_INVALID) {
Info.CondBrs.clear();
Info.UncondBr = &MI;
continue;
@@ -789,7 +789,7 @@ X86SpeculativeLoadHardeningPass::tracePr
MachineBasicBlock &Succ = *CondBr->getOperand(0).getMBB();
int &SuccCount = SuccCounts[&Succ];
- X86::CondCode Cond = X86::getCondFromBranchOpc(CondBr->getOpcode());
+ X86::CondCode Cond = X86::getCondFromBranch(*CondBr);
X86::CondCode InvCond = X86::GetOppositeBranchCondition(Cond);
UncondCodeSeq.push_back(Cond);
Modified: llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/auto-successor.mir Fri Apr 5 12:28:09 2019
@@ -4,28 +4,28 @@
# CHECK-LABEL: name: func0
# CHECK: bb.0:
# CHECK-NOT: successors
-# CHECK: JE_1 %bb.1, implicit undef $eflags
+# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
# CHECK: JMP_1 %bb.3
# CHECK: bb.1:
# CHECK-NOT: successors
# CHECK: bb.2:
# CHECK-NOT: successors
-# CHECK: JE_1 %bb.1, implicit undef $eflags
+# CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
# CHECK: bb.3:
# CHECK: RETQ undef $eax
name: func0
body: |
bb.0:
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.3
bb.1:
bb.2:
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
bb.3:
- JE_1 %bb.4, implicit undef $eflags ; condjump+fallthrough to same block
+ JCC_1 %bb.4, 4, implicit undef $eflags ; condjump+fallthrough to same block
bb.4:
RETQ undef $eax
@@ -39,20 +39,20 @@ body: |
; CHECK: bb.0:
; CHECK: successors: %bb.3, %bb.1
successors: %bb.3, %bb.1 ; different order than operands
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.3
bb.1:
; CHECK: bb.1:
; CHECK: successors: %bb.2, %bb.1
successors: %bb.2, %bb.1 ; different order (fallthrough variant)
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
bb.2:
; CHECK: bb.2:
; CHECK: successors: %bb.1(0x60000000), %bb.3(0x20000000)
successors: %bb.1(3), %bb.3(1) ; branch probabilities not normalized
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
bb.3:
; CHECK: bb.3:
Modified: llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir Fri Apr 5 12:28:09 2019
@@ -26,7 +26,7 @@ body: |
liveins: $edi 44
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit killed $eflags
+ JCC_1 %bb.2.exit, 15, implicit killed $eflags
; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
less bb.1:
Modified: llvm/trunk/test/CodeGen/MIR/X86/branch-folder-with-label.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/branch-folder-with-label.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/branch-folder-with-label.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/branch-folder-with-label.mir Fri Apr 5 12:28:09 2019
@@ -235,8 +235,8 @@ body: |
renamable $edi = MOV32rm $rdi, 1, $noreg, 0, $noreg :: (load 4 from %ir.out)
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !9
TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
- JNS_1 %bb.2, implicit killed $eflags
- ; CHECK: JS_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 9, implicit killed $eflags
+ ; CHECK: JCC_1 %bb.2, 8, implicit $eflags
bb.1:
successors: %bb.3(0x80000000)
@@ -321,8 +321,8 @@ body: |
renamable $rdi = LEA64r $rsp, 1, $noreg, 4, $noreg
CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
- JNS_1 %bb.2, implicit killed $eflags
- ; CHECK: JS_1 %bb.5, implicit $eflags
+ JCC_1 %bb.2, 9, implicit killed $eflags
+ ; CHECK: JCC_1 %bb.5, 8, implicit $eflags
bb.1:
successors: %bb.5(0x80000000)
@@ -345,7 +345,7 @@ body: |
$rdi = COPY renamable $r14, debug-location !22
CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
- JNS_1 %bb.6, implicit killed $eflags
+ JCC_1 %bb.6, 9, implicit killed $eflags
bb.4:
successors: %bb.5(0x80000000)
@@ -368,7 +368,7 @@ body: |
liveins: $rbx, $r14
CMP32mi8 $rsp, 1, $noreg, 4, $noreg, 0, implicit-def $eflags :: (dereferenceable load 4 from %ir.idx)
- JS_1 %bb.8, implicit killed $eflags
+ JCC_1 %bb.8, 8, implicit killed $eflags
JMP_1 %bb.7
bb.7.lor.rhs:
@@ -376,7 +376,7 @@ body: |
liveins: $rbx, $r14
CMP32mi8 renamable $rbx, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.1)
- JNE_1 %bb.3, implicit killed $eflags
+ JCC_1 %bb.3, 5, implicit killed $eflags
JMP_1 %bb.8
bb.8.do.body.backedge:
@@ -386,7 +386,7 @@ body: |
$rdi = COPY renamable $r14, debug-location !22
CALL64pcrel32 @baz, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
TEST32rr renamable $eax, renamable $eax, implicit-def $eflags
- JNS_1 %bb.6, implicit killed $eflags
+ JCC_1 %bb.6, 9, implicit killed $eflags
bb.9:
successors: %bb.5(0x80000000)
Modified: llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/branch-probabilities.mir Fri Apr 5 12:28:09 2019
@@ -8,7 +8,7 @@ name: test
body: |
bb.0:
successors: %bb.1(4), %bb.2(1)
- JE_1 %bb.2, implicit undef $eflags
+ JCC_1 %bb.2, 4, implicit undef $eflags
bb.1:
NOOP
Modified: llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/callee-saved-info.mir Fri Apr 5 12:28:09 2019
@@ -75,7 +75,7 @@ body: |
liveins: $ebx
CMP32ri8 $ebx, 10, implicit-def $eflags
- JG_1 %bb.3.exit, implicit killed $eflags
+ JCC_1 %bb.3.exit, 15, implicit killed $eflags
JMP_1 %bb.2.loop
bb.2.loop:
Modified: llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir Fri Apr 5 12:28:09 2019
@@ -22,8 +22,8 @@ body: |
successors: %bb.1.less, %bb.2.exit
CMP32ri8 $edi, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
- JG_1 %bb.2.exit, implicit implicit $eflags
+ ; CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
+ JCC_1 %bb.2.exit, 15, implicit implicit $eflags
bb.1.less:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir Fri Apr 5 12:28:09 2019
@@ -26,7 +26,7 @@ body: |
liveins: $edi 44
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit killed $eflags
+ JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir Fri Apr 5 12:28:09 2019
@@ -23,8 +23,8 @@ body: |
bb.0.entry:
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:35: missing implicit register operand 'implicit $eflags'
- JG_1 %bb.2.exit, implicit $eax
+ ; CHECK: [[@LINE+1]]:40: missing implicit register operand 'implicit $eflags'
+ JCC_1 %bb.2.exit, 15, implicit $eax
bb.1.less:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir Fri Apr 5 12:28:09 2019
@@ -23,8 +23,8 @@ body: |
bb.0.entry:
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:42: missing implicit register operand 'implicit $eflags'
- JG_1 %bb.2.exit, implicit-def $eflags
+ ; CHECK: [[@LINE+1]]:47: missing implicit register operand 'implicit $eflags'
+ JCC_1 %bb.2.exit, 15, implicit-def $eflags
bb.1.less:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir Fri Apr 5 12:28:09 2019
@@ -24,7 +24,7 @@ body: |
liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit killed $eflags
+ JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir Fri Apr 5 12:28:09 2019
@@ -67,7 +67,7 @@ body: |
liveins: $ebx
CMP32ri8 $ebx, 10, implicit-def $eflags
- JG_1 %bb.3.exit, implicit killed $eflags
+ JCC_1 %bb.3.exit, 15, implicit killed $eflags
JMP_1 %bb.2.loop
bb.2.loop:
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir Fri Apr 5 12:28:09 2019
@@ -27,7 +27,7 @@ body: |
liveins: $edi 44
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit killed $eflags
+ JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-number-after-bb.mir Fri Apr 5 12:28:09 2019
@@ -22,8 +22,8 @@ body: |
bb.0.entry:
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
- JG_1 %bb.nah, implicit $eflags
+ ; CHECK: [[@LINE+1]]:15: expected a number after '%bb.'
+ JCC_1 %bb.nah, 15, implicit $eflags
bb.1.true:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/external-symbol-operands.mir Fri Apr 5 12:28:09 2019
@@ -40,7 +40,7 @@ body: |
$rax = MOVSX64rr32 $edi
$eax = MOV32rm $rsp, 4, $rax, 0, _
CMP64rm $rcx, $rsp, 1, _, 512, _, implicit-def $eflags
- JNE_1 %bb.2.entry, implicit $eflags
+ JCC_1 %bb.2.entry, 5, implicit $eflags
bb.1.entry:
liveins: $eax
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir Fri Apr 5 12:28:09 2019
@@ -47,7 +47,7 @@ body: |
$eax = COPY $edi
CMP32rr $eax, killed $esi, implicit-def $eflags
- JL_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 12, implicit killed $eflags
bb.1:
successors: %bb.3
Modified: llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/frame-info-stack-references.mir Fri Apr 5 12:28:09 2019
@@ -65,7 +65,7 @@ body: |
dead $eax = MOV32r0 implicit-def dead $eflags, implicit-def $al
CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $rsi, implicit $al, implicit-def $rsp, implicit-def $eax
CMP64rm killed $rbx, $rsp, 1, _, 24, _, implicit-def $eflags
- JNE_1 %bb.2.entry, implicit $eflags
+ JCC_1 %bb.2.entry, 5, implicit $eflags
bb.1.entry:
liveins: $eax
Modified: llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/implicit-register-flag.mir Fri Apr 5 12:28:09 2019
@@ -33,9 +33,9 @@ body: |
bb.0.entry:
successors: %bb.1, %bb.2
; CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
- ; CHECK-NEXT: JG_1 %bb.2, implicit $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 15, implicit $eflags
bb.1.less:
; CHECK: $eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/jump-table-info.mir Fri Apr 5 12:28:09 2019
@@ -74,7 +74,7 @@ body: |
$eax = MOV32rr $edi, implicit-def $rax
CMP32ri8 $edi, 3, implicit-def $eflags
- JA_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 7, implicit $eflags
bb.1.entry:
successors: %bb.3, %bb.4, %bb.5, %bb.6
@@ -117,7 +117,7 @@ body: |
$eax = MOV32rr $edi, implicit-def $rax
CMP32ri8 $edi, 3, implicit-def $eflags
- JA_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 7, implicit $eflags
bb.1.entry:
successors: %bb.3, %bb.4, %bb.5, %bb.6
Modified: llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir Fri Apr 5 12:28:09 2019
@@ -44,7 +44,7 @@ body: |
$eax = MOV32rr $edi, implicit-def $rax
CMP32ri8 $edi, 3, implicit-def $eflags
- JA_1 %bb.2.def, implicit $eflags
+ JCC_1 %bb.2.def, 7, implicit $eflags
bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
Modified: llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/killed-register-flag.mir Fri Apr 5 12:28:09 2019
@@ -24,7 +24,7 @@ body: |
successors: %bb.1.less, %bb.2.exit
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit $eflags
+ JCC_1 %bb.2.exit, 15, implicit $eflags
bb.1.less:
; CHECK: $eax = MOV32r0
Modified: llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/large-index-number-error.mir Fri Apr 5 12:28:09 2019
@@ -22,8 +22,8 @@ body: |
bb.0.entry:
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)
- JG_1 %bb.123456789123456, implicit $eflags
+ ; CHECK: [[@LINE+1]]:11: expected 32-bit integer (too large)
+ JCC_1 %bb.123456789123456, 15, implicit $eflags
bb.1:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/machine-basic-block-operands.mir Fri Apr 5 12:28:09 2019
@@ -40,9 +40,9 @@ body: |
$eax = MOV32rm $rdi, 1, _, 0, _
; CHECK: CMP32ri8 $eax, 10
- ; CHECK-NEXT: JG_1 %bb.2
+ ; CHECK-NEXT: JCC_1 %bb.2, 15
CMP32ri8 $eax, 10, implicit-def $eflags
- JG_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 15, implicit $eflags
; CHECK: bb.1.less:
bb.1.less:
@@ -61,9 +61,9 @@ body: |
$eax = MOV32rm $rdi, 1, _, 0, _
; CHECK: CMP32ri8 $eax, 10
- ; CHECK-NEXT: JG_1 %bb.2
+ ; CHECK-NEXT: JCC_1 %bb.2, 15
CMP32ri8 $eax, 10, implicit-def $eflags
- JG_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 15, implicit $eflags
bb.1:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/memory-operands.mir Fri Apr 5 12:28:09 2019
@@ -409,7 +409,7 @@ body: |
$eax = MOV32rr $edi, implicit-def $rax
CMP32ri8 killed $edi, 3, implicit-def $eflags
- JA_1 %bb.2.def, implicit killed $eflags
+ JCC_1 %bb.2.def, 7, implicit killed $eflags
bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
Modified: llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-implicit-operand.mir Fri Apr 5 12:28:09 2019
@@ -27,8 +27,8 @@ body: |
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:20: missing implicit register operand 'implicit $eflags'
- JG_1 %bb.2.exit
+ ; CHECK: [[@LINE+1]]:25: missing implicit register operand 'implicit $eflags'
+ JCC_1 %bb.2.exit, 15
bb.1.less:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/newline-handling.mir Fri Apr 5 12:28:09 2019
@@ -38,7 +38,7 @@ liveins:
# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
# CHECK-NEXT: liveins: $edi
# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
-# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
# CHECK: bb.1.less:
# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
@@ -56,7 +56,7 @@ body: |
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 15, implicit killed $eflags
bb.1.less:
@@ -82,7 +82,7 @@ liveins:
# CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
# CHECK-NEXT: liveins: $edi
# CHECK: CMP32ri8 $edi, 10, implicit-def $eflags
-# CHECK-NEXT: JG_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 15, implicit killed $eflags
# CHECK: bb.1.less:
# CHECK-NEXT: $eax = MOV32r0 implicit-def dead $eflags
@@ -98,7 +98,7 @@ body: |
successors: %bb.1, %bb.2
liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 15, implicit killed $eflags
bb.1.less: $eax = MOV32r0 implicit-def dead $eflags
RETQ killed $eax
Modified: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir Fri Apr 5 12:28:09 2019
@@ -28,7 +28,7 @@ body: |
liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 15, implicit killed $eflags
bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/successor-basic-blocks.mir Fri Apr 5 12:28:09 2019
@@ -38,7 +38,7 @@ body: |
liveins: $edi
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit killed $eflags
+ JCC_1 %bb.2.exit, 15, implicit killed $eflags
bb.1.less:
$eax = MOV32r0 implicit-def dead $eflags
@@ -64,7 +64,7 @@ body: |
successors: %bb.2
CMP32ri8 $edi, 10, implicit-def $eflags
- JG_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 15, implicit killed $eflags
; Verify that we can have an empty list of successors.
; CHECK-LABEL: bb.1:
Modified: llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/undefined-jump-table-id.mir Fri Apr 5 12:28:09 2019
@@ -41,7 +41,7 @@ body: |
$eax = MOV32rr $edi, implicit-def $rax
CMP32ri8 $edi, 3, implicit-def $eflags
- JA_1 %bb.2.def, implicit $eflags
+ JCC_1 %bb.2.def, 7, implicit $eflags
bb.1.entry:
successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir Fri Apr 5 12:28:09 2019
@@ -25,8 +25,8 @@ body: |
bb.0.entry:
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:10: use of undefined machine basic block #4
- JG_1 %bb.4, implicit $eflags
+ ; CHECK: [[@LINE+1]]:11: use of undefined machine basic block #4
+ JCC_1 %bb.4, 15, implicit $eflags
bb.1:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir Fri Apr 5 12:28:09 2019
@@ -24,8 +24,8 @@ body: |
bb.0.entry:
$eax = MOV32rm $rdi, 1, _, 0, _
CMP32ri8 $eax, 10, implicit-def $eflags
- ; CHECK: [[@LINE+1]]:10: the name of machine basic block #2 isn't 'hit'
- JG_1 %bb.2.hit, implicit $eflags
+ ; CHECK: [[@LINE+1]]:11: the name of machine basic block #2 isn't 'hit'
+ JCC_1 %bb.2.hit, 15, implicit $eflags
bb.1.less:
$eax = MOV32r0 implicit-def $eflags
Modified: llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/X86/virtual-registers.mir Fri Apr 5 12:28:09 2019
@@ -48,7 +48,7 @@ body: |
; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
%0 = COPY $edi
%1 = SUB32ri8 %0, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit $eflags
+ JCC_1 %bb.2.exit, 15, implicit $eflags
JMP_1 %bb.1.less
bb.1.less:
@@ -82,7 +82,7 @@ body: |
; CHECK-NEXT: %1:gr32 = SUB32ri8 %0, 10
%2 = COPY $edi
%0 = SUB32ri8 %2, 10, implicit-def $eflags
- JG_1 %bb.2.exit, implicit $eflags
+ JCC_1 %bb.2.exit, 15, implicit $eflags
JMP_1 %bb.1.less
bb.1.less:
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-brcond.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-brcond.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-brcond.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-brcond.mir Fri Apr 5 12:28:09 2019
@@ -33,7 +33,7 @@ registers:
# CHECK-NEXT: %3:gr32 = MOV32ri 1
# CHECK-NEXT: %1:gr8 = COPY %0.sub_8bit
# CHECK-NEXT: TEST8ri %1, 1, implicit-def $eflags
-# CHECK-NEXT: JNE_1 %[[TRUE:bb.[0-9]+]], implicit $eflags
+# CHECK-NEXT: JCC_1 %[[TRUE:bb.[0-9]+]], 5, implicit $eflags
# CHECK-NEXT: JMP_1 %[[FALSE:bb.[0-9]+]]
# CHECK: [[TRUE]].{{[a-zA-Z0-9]+}}:
# CHECK-NEXT: $eax = COPY %2
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-phi.mir Fri Apr 5 12:28:09 2019
@@ -129,7 +129,7 @@ body: |
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JNE_1 %bb.2, implicit $eflags
+ ; ALL: JCC_1 %bb.2, 5, implicit $eflags
; ALL: bb.1.cond.false:
; ALL: successors: %bb.2(0x80000000)
; ALL: bb.2.cond.end:
@@ -188,7 +188,7 @@ body: |
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JNE_1 %bb.2, implicit $eflags
+ ; ALL: JCC_1 %bb.2, 5, implicit $eflags
; ALL: bb.1.cond.false:
; ALL: successors: %bb.2(0x80000000)
; ALL: bb.2.cond.end:
@@ -243,7 +243,7 @@ body: |
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JNE_1 %bb.1, implicit $eflags
+ ; ALL: JCC_1 %bb.1, 5, implicit $eflags
; ALL: JMP_1 %bb.2
; ALL: bb.1.cond.true:
; ALL: successors: %bb.3(0x80000000)
@@ -306,7 +306,7 @@ body: |
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JNE_1 %bb.1, implicit $eflags
+ ; ALL: JCC_1 %bb.1, 5, implicit $eflags
; ALL: JMP_1 %bb.2
; ALL: bb.1.cond.true:
; ALL: successors: %bb.3(0x80000000)
@@ -378,7 +378,7 @@ body: |
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JNE_1 %bb.2, implicit $eflags
+ ; ALL: JCC_1 %bb.2, 5, implicit $eflags
; ALL: bb.1.cond.false:
; ALL: successors: %bb.2(0x80000000)
; ALL: bb.2.cond.end:
@@ -439,7 +439,7 @@ body: |
; ALL: CMP32rr [[COPY]], [[MOV32r0_]], implicit-def $eflags
; ALL: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
; ALL: TEST8ri [[SETCCr]], 1, implicit-def $eflags
- ; ALL: JNE_1 %bb.2, implicit $eflags
+ ; ALL: JCC_1 %bb.2, 5, implicit $eflags
; ALL: bb.1.cond.false:
; ALL: successors: %bb.2(0x80000000)
; ALL: bb.2.cond.end:
Modified: llvm/trunk/test/CodeGen/X86/PR37310.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/PR37310.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/PR37310.mir (original)
+++ llvm/trunk/test/CodeGen/X86/PR37310.mir Fri Apr 5 12:28:09 2019
@@ -114,7 +114,7 @@ body: |
%0:gr32 = COPY $edi
%1:gr32 = SUB32ri8 %0, 3, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
JMP_1 %bb.1
bb.1.if.then:
Modified: llvm/trunk/test/CodeGen/X86/block-placement.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/block-placement.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/block-placement.mir (original)
+++ llvm/trunk/test/CodeGen/X86/block-placement.mir Fri Apr 5 12:28:09 2019
@@ -60,7 +60,7 @@ body: |
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
TEST8ri $sil, 1, implicit-def $eflags, implicit killed $esi
- JE_1 %bb.3, implicit killed $eflags
+ JCC_1 %bb.3, 4, implicit killed $eflags
bb.1.left:
successors: %bb.2(0x7ffff800), %bb.4(0x00000800)
Modified: llvm/trunk/test/CodeGen/X86/branchfolding-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/branchfolding-undef.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/branchfolding-undef.mir (original)
+++ llvm/trunk/test/CodeGen/X86/branchfolding-undef.mir Fri Apr 5 12:28:09 2019
@@ -16,7 +16,7 @@ name: func
tracksRegLiveness: true
body: |
bb.0:
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.2
bb.1:
Modified: llvm/trunk/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir (original)
+++ llvm/trunk/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir Fri Apr 5 12:28:09 2019
@@ -7,7 +7,7 @@
name: foo
body: |
bb.0:
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.1:
CFI_INSTRUCTION def_cfa_offset 24
bb.2:
Modified: llvm/trunk/test/CodeGen/X86/cfi-inserter-noreturnblock.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cfi-inserter-noreturnblock.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cfi-inserter-noreturnblock.mir (original)
+++ llvm/trunk/test/CodeGen/X86/cfi-inserter-noreturnblock.mir Fri Apr 5 12:28:09 2019
@@ -8,7 +8,7 @@ name: testNoreturnBlock
body: |
bb.0:
CFI_INSTRUCTION def_cfa_offset 24
- JNE_1 %bb.2, implicit undef $eflags
+ JCC_1 %bb.2, 5, implicit undef $eflags
bb.1:
CFI_INSTRUCTION def_cfa_offset 32
Modified: llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir (original)
+++ llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir Fri Apr 5 12:28:09 2019
@@ -16,7 +16,7 @@ name: inconsistentOffset
body: |
bb.0:
CFI_INSTRUCTION def_cfa_offset 24
- JNE_1 %bb.2, implicit undef $eflags
+ JCC_1 %bb.2, 5, implicit undef $eflags
bb.1:
CFI_INSTRUCTION def_cfa_offset 32
Modified: llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir (original)
+++ llvm/trunk/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir Fri Apr 5 12:28:09 2019
@@ -16,7 +16,7 @@ name: inconsistentRegister
body: |
bb.0:
CFI_INSTRUCTION def_cfa_register $rbp
- JNE_1 %bb.2, implicit undef $eflags
+ JCC_1 %bb.2, 5, implicit undef $eflags
bb.1:
CFI_INSTRUCTION def_cfa $rsp, 8
Modified: llvm/trunk/test/CodeGen/X86/cmovcmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmovcmov.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmovcmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmovcmov.ll Fri Apr 5 12:28:09 2019
@@ -312,9 +312,9 @@ attributes #0 = { nounwind }
;
; The first two cmovs got expanded to:
; %bb.0:
-; JL_1 %bb.9
+; JCC_1 %bb.9, 12
; %bb.7:
-; JG_1 %bb.9
+; JCC_1 %bb.9, 15
; %bb.8:
; %bb.9:
; %12 = phi(%7, %bb.8, %11, %bb.0, %12, %bb.7)
Modified: llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir (original)
+++ llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir Fri Apr 5 12:28:09 2019
@@ -105,14 +105,14 @@ body: |
liveins: $edi
CMP32ri8 killed $edi, 2, implicit-def $eflags
- JB_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 2, implicit $eflags
JMP_1 %bb.1
bb.1.entry:
successors: %bb.4(0x40000000), %bb.5(0x40000000)
liveins: $eflags
- JE_1 %bb.4, implicit killed $eflags
+ JCC_1 %bb.4, 4, implicit killed $eflags
JMP_1 %bb.5
bb.2.sw.bb:
@@ -120,7 +120,7 @@ body: |
$al = MOV8rm $rip, 1, $noreg, @static_local_guard, $noreg :: (volatile load acquire 1 from `i8* bitcast (i64* @static_local_guard to i8*)`, align 8)
TEST8rr killed $al, $al, implicit-def $eflags
- JNE_1 %bb.6, implicit killed $eflags
+ JCC_1 %bb.6, 5, implicit killed $eflags
JMP_1 %bb.3
bb.3.init.check.i:
Modified: llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir Fri Apr 5 12:28:09 2019
@@ -78,7 +78,7 @@
# CHECK: bb.10.for.body.9
# CHECK: renamable $al
# CHECK-NEXT: TEST8rr killed renamable $al
-# CHECK-NEXT: JNE_1
+# CHECK-NEXT: JCC_1
# CHECK-NOT: $al = IMPLICIT_DEF
# CHECK: bb.12.for.body.10
@@ -93,7 +93,7 @@ body: |
renamable $al = MOV8ri 1
TEST8rr renamable $al, renamable $al, implicit-def $eflags
- JNE_1 %bb.4, implicit killed $eflags
+ JCC_1 %bb.4, 5, implicit killed $eflags
bb.1.for.cond.cleanup:
successors: %bb.3, %bb.2
@@ -101,7 +101,7 @@ body: |
renamable $eax = MOV32rm $rsp, 1, $noreg, -16, $noreg
CMP32rm killed renamable $eax, $rip, 1, $noreg, $noreg, $noreg, implicit-def $eflags
- JBE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 6, implicit $eflags
bb.2:
successors: %bb.3
@@ -117,7 +117,7 @@ body: |
renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.5.for.body.1:
successors: %bb.1, %bb.6
@@ -125,13 +125,13 @@ body: |
renamable $al = MOV8ri 1
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.6.for.body.2:
successors: %bb.1, %bb.7
liveins: $ecx, $eflags, $rdi
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.7.for.body.3:
successors: %bb.1, %bb.8
@@ -139,13 +139,13 @@ body: |
renamable $al = MOV8ri 1
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.8.for.body.4:
successors: %bb.1, %bb.9
liveins: $ecx, $eflags, $rdi
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.9.for.body.5:
successors: %bb.1, %bb.10
@@ -153,13 +153,13 @@ body: |
renamable $al = MOV8ri 1
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.10.for.body.6:
successors: %bb.1, %bb.11
liveins: $ecx, $eflags, $rdi
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.11.for.body.7:
successors: %bb.1, %bb.12
@@ -167,13 +167,13 @@ body: |
renamable $al = MOV8ri 1
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.12.for.body.8:
successors: %bb.1, %bb.13
liveins: $ecx, $eflags, $rdi
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 5, implicit $eflags
bb.13.for.body.9:
successors: %bb.14, %bb.15
@@ -181,7 +181,7 @@ body: |
renamable $al = MOV8ri 1
TEST8rr killed renamable $al, renamable $al, implicit-def $eflags
- JE_1 %bb.15, implicit $eflags
+ JCC_1 %bb.15, 4, implicit $eflags
bb.14:
successors: %bb.1
@@ -194,7 +194,7 @@ body: |
successors: %bb.16, %bb.17
liveins: $eflags, $rdi
- JE_1 %bb.17, implicit killed $eflags
+ JCC_1 %bb.17, 4, implicit killed $eflags
bb.16:
successors: %bb.1
Modified: llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/debugloc-no-line-0.ll Fri Apr 5 12:28:09 2019
@@ -7,7 +7,7 @@
; CHECK: JMP{{.*}}%bb.4, debug-location ![[JUMPLOC:[0-9]+]]
; CHECK: bb.4.entry:
; CHECK: successors:
-; CHECK: JE{{.*}}debug-location ![[JUMPLOC]]
+; CHECK: JCC{{.*}}debug-location ![[JUMPLOC]]
; CHECK: JMP{{.*}}debug-location ![[JUMPLOC]]
define i32 @main() !dbg !12 {
Modified: llvm/trunk/test/CodeGen/X86/domain-reassignment.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/domain-reassignment.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/domain-reassignment.mir (original)
+++ llvm/trunk/test/CodeGen/X86/domain-reassignment.mir Fri Apr 5 12:28:09 2019
@@ -123,7 +123,7 @@ body: |
; CHECK: [[COPY7:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY8:%[0-9]+]]:gr8 = COPY [[COPY7]].sub_8bit
; CHECK: TEST8ri killed [[COPY8]], 1, implicit-def $eflags
- ; CHECK: JE_1 %bb.2, implicit $eflags
+ ; CHECK: JCC_1 %bb.2, 4, implicit $eflags
; CHECK: JMP_1 %bb.1
; CHECK: bb.1.if:
; CHECK: successors: %bb.3(0x80000000)
@@ -160,7 +160,7 @@ body: |
%3 = COPY $edi
%11 = COPY %3.sub_8bit
TEST8ri killed %11, 1, implicit-def $eflags
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
JMP_1 %bb.1
bb.1.if:
@@ -310,7 +310,7 @@ body: |
; FIXME We can't replace TEST with KTEST due to flag differences
; TEST8rr %18, %18, implicit-def $eflags
- ; JE_1 %bb.1, implicit $eflags
+ ; JCC_1 %bb.1, 4, implicit $eflags
; JMP_1 %bb.2
bb.1:
@@ -427,7 +427,7 @@ body: |
; FIXME We can't replace TEST with KTEST due to flag differences
; FIXME TEST16rr %17, %17, implicit-def $eflags
- ; FIXME JE_1 %bb.1, implicit $eflags
+ ; FIXME JCC_1 %bb.1, 4, implicit $eflags
; FIXME JMP_1 %bb.2
bb.1:
@@ -530,7 +530,7 @@ body: |
; FIXME We can't replace TEST with KTEST due to flag differences
; FIXME TEST32rr %13, %13, implicit-def $eflags
- ; FIXME JE_1 %bb.1, implicit $eflags
+ ; FIXME JCC_1 %bb.1, 4, implicit $eflags
; FIXME JMP_1 %bb.2
bb.1:
@@ -633,7 +633,7 @@ body: |
; FIXME We can't replace TEST with KTEST due to flag differences
; FIXME TEST64rr %13, %13, implicit-def $eflags
- ; FIXME JE_1 %bb.1, implicit $eflags
+ ; FIXME JCC_1 %bb.1, 4, implicit $eflags
; FIXME JMP_1 %bb.2
bb.1:
Modified: llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir (original)
+++ llvm/trunk/test/CodeGen/X86/fixup-bw-inst.mir Fri Apr 5 12:28:09 2019
@@ -97,7 +97,7 @@ body: |
liveins: $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
bb.2.if.then:
liveins: $rdi
Modified: llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir (original)
+++ llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir Fri Apr 5 12:28:09 2019
@@ -128,19 +128,19 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
$eflags = COPY %2
- JA_1 %bb.1, implicit $eflags
- JB_1 %bb.2, implicit $eflags
+ JCC_1 %bb.1, 7, implicit $eflags
+ JCC_1 %bb.2, 2, implicit $eflags
JMP_1 %bb.3
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: {{.*$}}
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.3
bb.1:
@@ -184,18 +184,18 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
$eflags = COPY %2
- JA_1 %bb.2, implicit $eflags
- JB_1 %bb.3, implicit $eflags
+ JCC_1 %bb.2, 7, implicit $eflags
+ JCC_1 %bb.3, 2, implicit $eflags
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: {{.*$}}
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.3, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.3, 5, implicit killed $eflags
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: bb.1:
@@ -610,19 +610,19 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
$eflags = COPY %2
- JA_1 %bb.1, implicit $eflags
- JB_1 %bb.2, implicit $eflags
+ JCC_1 %bb.1, 7, implicit $eflags
+ JCC_1 %bb.2, 2, implicit $eflags
JMP_1 %bb.3
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: {{.*$}}
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.3
bb.1:
@@ -685,19 +685,19 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
$eflags = COPY %2
- JA_1 %bb.1, implicit $eflags
- JB_1 %bb.2, implicit $eflags
+ JCC_1 %bb.1, 7, implicit $eflags
+ JCC_1 %bb.2, 2, implicit $eflags
JMP_1 %bb.5
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: bb.6:
; CHECK-NEXT: successors: {{.*$}}
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.5
bb.1:
@@ -717,12 +717,12 @@ body: |
successors: %bb.3, %bb.4
liveins: $eflags
- JO_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 0, implicit $eflags
JMP_1 %bb.4
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[O_REG]], %[[O_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.3, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.3, 5, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.4
bb.3:
@@ -820,7 +820,7 @@ body: |
liveins: $eflags
; Outer loop header, target for one set of hoisting.
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
JMP_1 %bb.4
; CHECK: bb.1:
; CHECK-NOT: COPY{{( killed)?}} $eflags
@@ -836,12 +836,12 @@ body: |
; Inner loop with a local copy. We should eliminate this but can't hoist.
%2:gr64 = COPY $eflags
$eflags = COPY %2
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
JMP_1 %bb.3
; CHECK: bb.2:
; CHECK-NOT: COPY{{( killed)?}} $eflags
; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.2, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 5, implicit killed $eflags
; CHECK-NOT: COPY{{( killed)?}} $eflags
bb.3:
@@ -863,12 +863,12 @@ body: |
liveins: $eflags
; Another inner loop, this one with a diamond.
- JE_1 %bb.5, implicit $eflags
+ JCC_1 %bb.5, 4, implicit $eflags
JMP_1 %bb.6
; CHECK: bb.4:
; CHECK-NOT: COPY{{( killed)?}} $eflags
; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.5, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.5, 5, implicit killed $eflags
; CHECK-NOT: COPY{{( killed)?}} $eflags
bb.5:
@@ -914,12 +914,12 @@ body: |
liveins: $eflags
; Inner loop latch.
- JE_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 4, implicit $eflags
JMP_1 %bb.8
; CHECK: bb.7:
; CHECK-NOT: COPY{{( killed)?}} $eflags
; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.4, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed $eflags
; CHECK-NOT: COPY{{( killed)?}} $eflags
bb.8:
@@ -928,12 +928,12 @@ body: |
; Outer loop latch. Note that we cannot have EFLAGS live-in here as that
; immediately require PHIs.
CMP64rr %0, %1, implicit-def $eflags
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
JMP_1 %bb.9
; CHECK: bb.8:
; CHECK-NOT: COPY{{( killed)?}} $eflags
; CHECK: CMP64rr %0, %1, implicit-def $eflags
- ; CHECK-NEXT: JE_1 %bb.1, implicit $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
; CHECK-NOT: COPY{{( killed)?}} $eflags
bb.9:
@@ -975,19 +975,19 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
$eflags = COPY %4
- JA_1 %bb.1, implicit $eflags
- JB_1 %bb.2, implicit $eflags
+ JCC_1 %bb.1, 7, implicit $eflags
+ JCC_1 %bb.2, 2, implicit $eflags
JMP_1 %bb.3
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: {{.*$}}
; CHECK-SAME: {{$[[:space:]]}}
; CHECK-NEXT: TEST8rr %[[AE_REG]], %[[AE_REG]], implicit-def $eflags
- ; CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.3
bb.1:
@@ -1036,12 +1036,12 @@ body: |
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
$eflags = COPY %2
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
JMP_1 %bb.2
; CHECK-NOT: $eflags =
;
; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def $eflags
- ; CHECK-NEXT: JNE_1 %bb.1, implicit killed $eflags
+ ; CHECK-NEXT: JCC_1 %bb.1, 5, implicit killed $eflags
; CHECK-NEXT: JMP_1 %bb.2
bb.1:
Modified: llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir (original)
+++ llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir Fri Apr 5 12:28:09 2019
@@ -399,7 +399,7 @@ body: |
liveins: $esi, $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.1.not_null:
liveins: $esi, $rdi
@@ -407,7 +407,7 @@ body: |
$eax = MOV32ri 2200000
$eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
CMP32rr killed $eax, killed $esi, implicit-def $eflags
- JE_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200:
$eax = MOV32ri 200
@@ -433,7 +433,7 @@ liveins:
# CHECK: bb.0.entry:
# CHECK: $eax = MOV32rm killed $rdx, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.ptr)
# CHECK-NEXT: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.3, implicit $eflags
+# CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
body: |
bb.0.entry:
@@ -441,7 +441,7 @@ body: |
$eax = MOV32rm killed $rdx, 1, $noreg, 0, $noreg :: (volatile load 4 from %ir.ptr)
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.1.not_null:
liveins: $esi, $rdi
@@ -449,7 +449,7 @@ body: |
$eax = MOV32ri 2200000
$eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
CMP32rr killed $eax, killed $esi, implicit-def $eflags
- JE_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200:
@@ -475,14 +475,14 @@ liveins:
- { reg: '$esi' }
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.3, implicit $eflags
+# CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
body: |
bb.0.entry:
liveins: $esi, $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.1.not_null:
liveins: $esi, $rdi
@@ -491,7 +491,7 @@ body: |
$eax = ADD32ri killed $eax, 100, implicit-def dead $eflags
$eax = AND32rm killed $eax, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
CMP32rr killed $eax, killed $esi, implicit-def $eflags
- JE_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200:
$eax = MOV32ri 200
@@ -516,14 +516,14 @@ liveins:
- { reg: '$rsi' }
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.3, implicit $eflags
+# CHECK-NEXT: JCC_1 %bb.3, 4, implicit $eflags
body: |
bb.0.entry:
liveins: $rsi, $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.1.not_null:
liveins: $rsi, $rdi
@@ -531,7 +531,7 @@ body: |
$rdi = MOV64ri 5000
$rdi = AND64rm killed $rdi, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
CMP64rr killed $rdi, killed $rsi, implicit-def $eflags
- JE_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200:
$eax = MOV32ri 200
@@ -563,7 +563,7 @@ body: |
liveins: $rsi, $rdi, $rdx
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.1.not_null:
liveins: $rsi, $rdi, $rdx
@@ -572,7 +572,7 @@ body: |
$rbx = AND64rm killed $rbx, killed $rdi, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load 4 from %ir.x)
$rdx = MOV64ri 0
CMP64rr killed $rbx, killed $rsi, implicit-def $eflags
- JE_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 4, implicit $eflags
bb.2.ret_200:
$eax = MOV32ri 200
@@ -611,7 +611,7 @@ body: |
CFI_INSTRUCTION offset $rbx, -16
$rbx = MOV64rr $rdi
TEST64rr $rbx, $rbx, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.stay:
liveins: $rbx
@@ -648,7 +648,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -682,7 +682,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -713,7 +713,7 @@ body: |
liveins: $rsi, $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
bb.2.not_null:
liveins: $rdi, $rsi
@@ -745,7 +745,7 @@ body: |
liveins: $rsi, $rdi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
bb.2.not_null:
liveins: $rdi, $rsi
@@ -778,7 +778,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -808,7 +808,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -839,7 +839,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -857,7 +857,7 @@ name: inc_store_with_dep_in_n
# CHECK-LABEL: inc_store_with_dep_in_null
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -870,7 +870,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -892,7 +892,7 @@ name: inc_store_with_volatile
# CHECK-LABEL: inc_store_with_volatile
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -905,7 +905,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -922,7 +922,7 @@ name: inc_store_with_two_dep
# CHECK-LABEL: inc_store_with_two_dep
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -935,7 +935,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -954,7 +954,7 @@ name: inc_store_with_redefine
# CHECK-LABEL: inc_store_with_redefined_base
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -967,7 +967,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -998,7 +998,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1017,7 +1017,7 @@ name: inc_store_across_call
# CHECK-LABEL: inc_store_across_call
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rbx, $rbx, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1037,7 +1037,7 @@ body: |
CFI_INSTRUCTION offset $rbx, -16
$rbx = MOV64rr killed $rdi
TEST64rr $rbx, $rbx, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rbx
@@ -1059,7 +1059,7 @@ name: inc_store_with_dep_in_d
# CHECK-LABEL: inc_store_with_dep_in_dep
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1072,7 +1072,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1092,7 +1092,7 @@ name: inc_store_with_load_ove
# CHECK-LABEL: inc_store_with_load_over_store
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1105,7 +1105,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1124,7 +1124,7 @@ name: inc_store_with_store_ov
# CHECK-LABEL: inc_store_with_store_over_load
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1137,7 +1137,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1156,7 +1156,7 @@ name: inc_store_with_store_ov
# CHECK-LABEL: inc_store_with_store_over_store
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1169,7 +1169,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1200,7 +1200,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1231,7 +1231,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1250,7 +1250,7 @@ name: inc_store_and_load_alia
# CHECK-LABEL: inc_store_and_load_alias
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1263,7 +1263,7 @@ body: |
liveins: $rdi, $rsi
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
@@ -1282,7 +1282,7 @@ name: inc_spill_dep
# CHECK-LABEL: inc_spill_dep
# CHECK: bb.0.entry:
# CHECK: TEST64rr $rdi, $rdi, implicit-def $eflags
-# CHECK-NEXT: JE_1 %bb.2, implicit killed $eflags
+# CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags
# CHECK: bb.1.not_null
alignment: 4
@@ -1299,7 +1299,7 @@ body: |
$rsp = frame-setup SUB64ri8 $rsp, 8, implicit-def dead $eflags
MOV32mr $rsp, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.0)
TEST64rr $rdi, $rdi, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
bb.1.not_null:
liveins: $rdi, $rsi
Modified: llvm/trunk/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir (original)
+++ llvm/trunk/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir Fri Apr 5 12:28:09 2019
@@ -35,7 +35,7 @@ body: |
; CHECK-LABEL: bb.0.entry
; CHECK-NOT: FAULTING_OP
renamable $rdi = MOV64ri 5000
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
bb.1.not_null:
liveins: $rdi, $rsi
Modified: llvm/trunk/test/CodeGen/X86/invalid-liveness.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/invalid-liveness.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/invalid-liveness.mir (original)
+++ llvm/trunk/test/CodeGen/X86/invalid-liveness.mir Fri Apr 5 12:28:09 2019
@@ -16,7 +16,7 @@ registers:
- { id: 0, class: gr32 }
body: |
bb.0:
- JG_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 15, implicit $eflags
JMP_1 %bb.3
bb.2:
Modified: llvm/trunk/test/CodeGen/X86/late-remat-update-2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/late-remat-update-2.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/late-remat-update-2.mir (original)
+++ llvm/trunk/test/CodeGen/X86/late-remat-update-2.mir Fri Apr 5 12:28:09 2019
@@ -38,7 +38,7 @@ body: |
%t1:gr64 = MOV64ri32 -11
CMP64ri8 %t1, 1, implicit-def $eflags
- JE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 4, implicit killed $eflags
JMP_1 %bb.1
bb.1:
@@ -48,7 +48,7 @@ body: |
%t2:gr64 = ADD64ri8 %t2, 5, implicit-def $eflags
$rax = COPY %t2
CMP64ri8 %t2, 1, implicit-def $eflags
- JE_1 %bb.1, implicit killed $eflags
+ JCC_1 %bb.1, 4, implicit killed $eflags
RET 0, $rax
bb.2:
Modified: llvm/trunk/test/CodeGen/X86/late-remat-update.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/late-remat-update.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/late-remat-update.mir (original)
+++ llvm/trunk/test/CodeGen/X86/late-remat-update.mir Fri Apr 5 12:28:09 2019
@@ -79,21 +79,21 @@ body: |
INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
CMP32ri8 %0, 2, implicit-def $eflags
- JE_1 %bb.6, implicit killed $eflags
+ JCC_1 %bb.6, 4, implicit killed $eflags
JMP_1 %bb.2
bb.2.do.body:
successors: %bb.5(0x19999999), %bb.3(0x66666667)
CMP32ri8 %0, 1, implicit-def $eflags
- JE_1 %bb.5, implicit killed $eflags
+ JCC_1 %bb.5, 4, implicit killed $eflags
JMP_1 %bb.3
bb.3.do.body:
successors: %bb.4(0x20000000), %bb.1(0x60000000)
TEST32rr %0, %0, implicit-def $eflags
- JNE_1 %bb.1, implicit killed $eflags
+ JCC_1 %bb.1, 5, implicit killed $eflags
JMP_1 %bb.4
bb.4.sw.bb:
Modified: llvm/trunk/test/CodeGen/X86/leaFixup32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/leaFixup32.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/leaFixup32.mir (original)
+++ llvm/trunk/test/CodeGen/X86/leaFixup32.mir Fri Apr 5 12:28:09 2019
@@ -496,7 +496,7 @@ body: |
CMP32rr $eax, killed $ebx, implicit-def $eflags
$ebx = LEA32r killed $eax, 4, killed $eax, 5, $noreg
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
RETQ $ebx
bb.1:
liveins: $eax, $ebp, $ebx
Modified: llvm/trunk/test/CodeGen/X86/leaFixup64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/leaFixup64.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/leaFixup64.mir (original)
+++ llvm/trunk/test/CodeGen/X86/leaFixup64.mir Fri Apr 5 12:28:09 2019
@@ -952,7 +952,7 @@ body: |
CMP64rr $rax, killed $rbx, implicit-def $eflags
$rbx = LEA64r killed $rax, 4, killed $rax, 5, $noreg
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
RETQ $ebx
bb.1:
liveins: $rax, $rbp, $rbx
@@ -1028,7 +1028,7 @@ body: |
CMP64rr $rax, killed $rbx, implicit-def $eflags
$ebx = LEA64_32r killed $rax, 4, killed $rax, 5, $noreg
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
RETQ $ebx
bb.1:
liveins: $rax, $rbp, $rbx
Modified: llvm/trunk/test/CodeGen/X86/limit-split-cost.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/limit-split-cost.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/limit-split-cost.mir (original)
+++ llvm/trunk/test/CodeGen/X86/limit-split-cost.mir Fri Apr 5 12:28:09 2019
@@ -102,21 +102,21 @@ body: |
INLINEASM &"", 1, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $eflags, !3
CMP32ri8 %0, 2, implicit-def $eflags
- JE_1 %bb.6, implicit killed $eflags
+ JCC_1 %bb.6, 4, implicit killed $eflags
JMP_1 %bb.2
bb.2.do.body:
successors: %bb.5(0x2aaaaaab), %bb.3(0x55555555)
CMP32ri8 %0, 1, implicit-def $eflags
- JE_1 %bb.5, implicit killed $eflags
+ JCC_1 %bb.5, 4, implicit killed $eflags
JMP_1 %bb.3
bb.3.do.body:
successors: %bb.4, %bb.7
TEST32rr %0, %0, implicit-def $eflags
- JNE_1 %bb.7, implicit killed $eflags
+ JCC_1 %bb.7, 5, implicit killed $eflags
JMP_1 %bb.4
bb.4.sw.bb:
@@ -141,7 +141,7 @@ body: |
successors: %bb.8(0x04000000), %bb.1(0x7c000000)
CMP32mi8 %6, 1, $noreg, 0, $noreg, 5, implicit-def $eflags :: (dereferenceable load 4 from @m, !tbaa !4)
- JNE_1 %bb.1, implicit killed $eflags
+ JCC_1 %bb.1, 5, implicit killed $eflags
JMP_1 %bb.8
bb.8.do.end:
Modified: llvm/trunk/test/CodeGen/X86/machine-region-info.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-region-info.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-region-info.mir (original)
+++ llvm/trunk/test/CodeGen/X86/machine-region-info.mir Fri Apr 5 12:28:09 2019
@@ -5,29 +5,29 @@ name: fun
body: |
bb.0:
CMP32ri8 $edi, 40, implicit-def $eflags
- JNE_1 %bb.7, implicit killed $eflags
+ JCC_1 %bb.7, 5, implicit killed $eflags
JMP_1 %bb.1
bb.1:
CMP32ri8 $edi, 1, implicit-def $eflags
- JNE_1 %bb.11, implicit killed $eflags
+ JCC_1 %bb.11, 5, implicit killed $eflags
JMP_1 %bb.2
bb.2:
CMP32ri8 $edi, 2, implicit-def $eflags
- JNE_1 %bb.5, implicit killed $eflags
+ JCC_1 %bb.5, 5, implicit killed $eflags
JMP_1 %bb.3
bb.3:
CMP32ri8 $edi, 90, implicit-def $eflags
- JNE_1 %bb.5, implicit killed $eflags
+ JCC_1 %bb.5, 5, implicit killed $eflags
JMP_1 %bb.4
bb.4:
bb.5:
CMP32ri8 $edi, 4, implicit-def $eflags
- JNE_1 %bb.11, implicit killed $eflags
+ JCC_1 %bb.11, 5, implicit killed $eflags
JMP_1 %bb.6
bb.6:
@@ -35,14 +35,14 @@ body: |
bb.7:
CMP32ri8 $edi, 5, implicit-def $eflags
- JE_1 %bb.9, implicit killed $eflags
+ JCC_1 %bb.9, 4, implicit killed $eflags
JMP_1 %bb.8
bb.8:
bb.9:
CMP32ri8 $edi, 6, implicit-def $eflags
- JE_1 %bb.11, implicit killed $eflags
+ JCC_1 %bb.11, 4, implicit killed $eflags
JMP_1 %bb.10
bb.10:
Modified: llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir (original)
+++ llvm/trunk/test/CodeGen/X86/non-value-mem-operand.mir Fri Apr 5 12:28:09 2019
@@ -154,14 +154,14 @@ body: |
$rsp = frame-setup SUB64ri8 $rsp, 56, implicit-def dead $eflags
CALL64r undef $rax, csr_64, implicit $rsp, implicit undef $rdi, implicit undef $rsi, implicit-def $rsp, implicit-def $rax
TEST64rr $rax, $rax, implicit-def $eflags
- JNE_1 %bb.3.bb3, implicit killed $eflags
+ JCC_1 %bb.3.bb3, 5, implicit killed $eflags
bb.1.bb2:
successors: %bb.2(0x40000000), %bb.13.bb59(0x40000000)
$ebp = XOR32rr undef $ebp, undef $ebp, implicit-def dead $eflags
TEST8rr $bpl, $bpl, implicit-def $eflags
- JE_1 %bb.13.bb59, implicit killed $eflags
+ JCC_1 %bb.13.bb59, 4, implicit killed $eflags
bb.2:
successors: %bb.12.bb51(0x80000000)
@@ -194,7 +194,7 @@ body: |
$ebx = MOV32rr killed $eax, implicit-def $rbx
$r14d = MOV32rr $ebx, implicit-def $r14
TEST8rr $sil, $sil, implicit-def $eflags
- JNE_1 %bb.6.bb26, implicit $eflags
+ JCC_1 %bb.6.bb26, 5, implicit $eflags
bb.5.bb15:
successors: %bb.6.bb26(0x80000000)
@@ -227,7 +227,7 @@ body: |
$r13 = MOV64rm killed $rax, 1, $noreg, 768, $noreg :: (load 8 from %ir.tmp33)
TEST8rr $sil, $sil, implicit-def $eflags
$rax = IMPLICIT_DEF
- JNE_1 %bb.8.bb37, implicit $eflags
+ JCC_1 %bb.8.bb37, 5, implicit $eflags
bb.7.bb35:
successors: %bb.8.bb37(0x80000000)
@@ -244,7 +244,7 @@ body: |
$rcx = MOV64rm killed $rax, 1, $noreg, 760, $noreg :: (load 8 from %ir.tmp40)
CMP64rr $r13, $rcx, implicit-def $eflags
- JL_1 %bb.10.bb37, implicit $eflags
+ JCC_1 %bb.10.bb37, 12, implicit $eflags
bb.9.bb37:
successors: %bb.10.bb37(0x80000000)
@@ -264,7 +264,7 @@ body: |
$ecx = MOV32ri 6
CMP32ri $eax, 15141, implicit-def $eflags
$xmm0 = MOVSDrm $rsp, 1, $noreg, 40, $noreg :: (load 8 from %stack.4)
- JL_1 %bb.4.bb7, implicit $eflags
+ JCC_1 %bb.4.bb7, 12, implicit $eflags
bb.11.bb51.loopexit:
successors: %bb.12.bb51(0x80000000)
Modified: llvm/trunk/test/CodeGen/X86/opt_phis2.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/opt_phis2.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/opt_phis2.mir (original)
+++ llvm/trunk/test/CodeGen/X86/opt_phis2.mir Fri Apr 5 12:28:09 2019
@@ -30,7 +30,7 @@ body: |
%15:gr32 = SUB32rr %7, %14, implicit-def dead $eflags
%10:gr64_nosp = SUBREG_TO_REG 0, %15, %subreg.sub_32bit
%16:gr32 = SUB32ri8 %15, 3, implicit-def $eflags
- JA_1 %bb.8, implicit $eflags
+ JCC_1 %bb.8, 7, implicit $eflags
bb.9:
JMP64m $noreg, 8, %10, %jump-table.0, $noreg :: (load 8 from jump-table)
Modified: llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir (original)
+++ llvm/trunk/test/CodeGen/X86/peephole-recurrence.mir Fri Apr 5 12:28:09 2019
@@ -102,7 +102,7 @@ body: |
%0 = PHI %5, %bb.0, %3, %bb.5
%6 = MOV32ri 1
TEST32rr %4, %4, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
JMP_1 %bb.2
bb.2.bb3:
@@ -115,7 +115,7 @@ body: |
%1 = PHI %6, %bb.1, %7, %bb.2
TEST32rr %1, %1, implicit-def $eflags
- JE_1 %bb.5, implicit $eflags
+ JCC_1 %bb.5, 4, implicit $eflags
JMP_1 %bb.4
bb.4.bb6:
@@ -136,7 +136,7 @@ body: |
; CHECK-SAME: %10,
; CHECK-SAME: %2,
%11 = SUB32ri8 %3, 10, implicit-def $eflags
- JL_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 12, implicit $eflags
JMP_1 %bb.6
bb.6.bb8:
@@ -186,7 +186,7 @@ body: |
; CHECK: %0:gr32 = PHI %6, %bb.0, %3, %bb.5
%7 = MOV32ri 1
TEST32rr %4, %4, implicit-def $eflags
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
JMP_1 %bb.2
bb.2.bb3:
@@ -199,7 +199,7 @@ body: |
%1 = PHI %7, %bb.1, %8, %bb.2
TEST32rr %1, %1, implicit-def $eflags
- JE_1 %bb.5, implicit $eflags
+ JCC_1 %bb.5, 4, implicit $eflags
JMP_1 %bb.4
bb.4.bb6:
@@ -221,7 +221,7 @@ body: |
; CHECK-SAME: %2,
; CHECK-SAME: %11,
%12 = SUB32ri8 %3, 10, implicit-def $eflags
- JL_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 12, implicit $eflags
JMP_1 %bb.6
bb.6.bb8:
Modified: llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir (original)
+++ llvm/trunk/test/CodeGen/X86/post-ra-sched-with-debug.mir Fri Apr 5 12:28:09 2019
@@ -293,7 +293,7 @@ body: |
$rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags
$rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load 4, align 8)
TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load 4)
- JNE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 5, implicit $eflags
JMP_1 %bb.3
bb.1:
@@ -313,7 +313,7 @@ body: |
$eax = LEA64_32r killed $rax, 1, killed $rcx, -1, $noreg
$eax = SAR32r1 killed $eax, implicit-def dead $eflags
CMP32mr $rbx, 1, $noreg, 0, $noreg, killed $eax, implicit-def $eflags :: (load 4, align 8), (load 4, align 8)
- JG_1 %bb.1, implicit killed $eflags
+ JCC_1 %bb.1, 15, implicit killed $eflags
bb.3:
liveins: $rbp
Modified: llvm/trunk/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/postra-ignore-dbg-instrs.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/postra-ignore-dbg-instrs.mir (original)
+++ llvm/trunk/test/CodeGen/X86/postra-ignore-dbg-instrs.mir Fri Apr 5 12:28:09 2019
@@ -75,7 +75,7 @@ body: |
renamable $eax = COPY $edi
DBG_VALUE $eax, $noreg, !14, !DIExpression(), debug-location !16
CMP32mi8 $rip, 1, $noreg, @x0, $noreg, 0, implicit-def $eflags, debug-location !16
- JE_1 %bb.2, implicit killed $eflags, debug-location !16
+ JCC_1 %bb.2, 4, implicit killed $eflags, debug-location !16
JMP_1 %bb.1, debug-location !16
bb.1:
Modified: llvm/trunk/test/CodeGen/X86/pr27681.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr27681.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr27681.mir (original)
+++ llvm/trunk/test/CodeGen/X86/pr27681.mir Fri Apr 5 12:28:09 2019
@@ -61,7 +61,7 @@ body: |
$cl = AND8rr killed $cl, killed $bl, implicit-def dead $eflags
CMP32ri8 $ebp, -1, implicit-def $eflags
$edx = MOV32ri 0
- JE_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 4, implicit $eflags
bb.2:
liveins: $cl, $eax, $ebp, $esi
Modified: llvm/trunk/test/CodeGen/X86/pr38952.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38952.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr38952.mir (original)
+++ llvm/trunk/test/CodeGen/X86/pr38952.mir Fri Apr 5 12:28:09 2019
@@ -77,7 +77,7 @@ body: |
renamable $eax = MOV32r0 implicit-def dead $eflags
DBG_VALUE $ebx, $noreg, !21, !DIExpression()
CMP32ri $edi, 255, implicit-def $eflags
- JG_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 15, implicit killed $eflags
JMP_1 %bb.1
bb.1.if.end:
Modified: llvm/trunk/test/CodeGen/X86/pre-coalesce.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-coalesce.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-coalesce.mir (original)
+++ llvm/trunk/test/CodeGen/X86/pre-coalesce.mir Fri Apr 5 12:28:09 2019
@@ -43,7 +43,7 @@
# CHECK: [[L1:bb.3]].{{[a-zA-Z0-9.]+}}:
# CHECK: %[[REGA:.*]] = COPY %[[REGB:.*]]
# CHECK-NOT: %[[REGB]] = COPY %[[REGA]]
-# CHECK: JNE_1 %[[L1]]
+# CHECK: JCC_1 %[[L1]], 5
name: foo
alignment: 4
@@ -87,7 +87,7 @@ body: |
%12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
TEST8rr %12, %12, implicit-def $eflags
%11 = MOV32rm $rip, 1, $noreg, @a, $noreg :: (dereferenceable load 4 from @a)
- JNE_1 %bb.1, implicit killed $eflags
+ JCC_1 %bb.1, 5, implicit killed $eflags
bb.4:
%10 = COPY %11
@@ -105,7 +105,7 @@ body: |
%12 = MOV8rm %0, 1, $noreg, 0, $noreg :: (load 1 from %ir.t0)
TEST8rr %12, %12, implicit-def $eflags
%11 = COPY %10
- JNE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 5, implicit killed $eflags
JMP_1 %bb.3
bb.3.while.end:
Modified: llvm/trunk/test/CodeGen/X86/regalloc-copy-hints.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/regalloc-copy-hints.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/regalloc-copy-hints.mir (original)
+++ llvm/trunk/test/CodeGen/X86/regalloc-copy-hints.mir Fri Apr 5 12:28:09 2019
@@ -112,7 +112,7 @@ body: |
%13:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %13.sub_8bit, %13.sub_8bit, implicit-def $eflags
- JNE_1 %bb.2, implicit killed $eflags
+ JCC_1 %bb.2, 5, implicit killed $eflags
JMP_1 %bb.1
bb.1:
@@ -124,7 +124,7 @@ body: |
%15:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %15.sub_8bit, %15.sub_8bit, implicit-def $eflags
- JNE_1 %bb.4, implicit killed $eflags
+ JCC_1 %bb.4, 5, implicit killed $eflags
JMP_1 %bb.3
bb.3:
@@ -139,7 +139,7 @@ body: |
MOV32mr undef %17:gr32, 1, $noreg, 0, $noreg, %1
%18:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %18.sub_8bit, %18.sub_8bit, implicit-def $eflags
- JNE_1 %bb.6, implicit killed $eflags
+ JCC_1 %bb.6, 5, implicit killed $eflags
JMP_1 %bb.5
bb.5:
@@ -151,7 +151,7 @@ body: |
%20:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %20.sub_8bit, %20.sub_8bit, implicit-def $eflags
- JNE_1 %bb.8, implicit killed $eflags
+ JCC_1 %bb.8, 5, implicit killed $eflags
JMP_1 %bb.7
bb.7:
@@ -163,7 +163,7 @@ body: |
%22:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %22.sub_8bit, %22.sub_8bit, implicit-def $eflags
- JNE_1 %bb.10, implicit killed $eflags
+ JCC_1 %bb.10, 5, implicit killed $eflags
JMP_1 %bb.9
bb.9:
@@ -175,7 +175,7 @@ body: |
%24:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
- JNE_1 %bb.12, implicit killed $eflags
+ JCC_1 %bb.12, 5, implicit killed $eflags
JMP_1 %bb.11
bb.11:
@@ -187,7 +187,7 @@ body: |
%26:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %26.sub_8bit, %26.sub_8bit, implicit-def $eflags
- JNE_1 %bb.14, implicit killed $eflags
+ JCC_1 %bb.14, 5, implicit killed $eflags
JMP_1 %bb.13
bb.13:
@@ -198,7 +198,7 @@ body: |
%0:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
%28:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %28.sub_8bit, %28.sub_8bit, implicit-def $eflags
- JNE_1 %bb.20, implicit killed $eflags
+ JCC_1 %bb.20, 5, implicit killed $eflags
JMP_1 %bb.15
bb.15:
@@ -206,7 +206,7 @@ body: |
%78:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
- JNE_1 %bb.17, implicit killed $eflags
+ JCC_1 %bb.17, 5, implicit killed $eflags
JMP_1 %bb.16
bb.16:
@@ -217,7 +217,7 @@ body: |
successors: %bb.18(0x7fffffff), %bb.19(0x00000001)
TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
- JE_1 %bb.19, implicit killed $eflags
+ JCC_1 %bb.19, 4, implicit killed $eflags
bb.18:
%79:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
@@ -237,7 +237,7 @@ body: |
%35:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %35.sub_8bit, %35.sub_8bit, implicit-def $eflags
%80:gr32 = IMPLICIT_DEF
- JNE_1 %bb.23, implicit killed $eflags
+ JCC_1 %bb.23, 5, implicit killed $eflags
JMP_1 %bb.22
bb.22:
@@ -257,7 +257,7 @@ body: |
MOV32mi %80, 1, $noreg, 52, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv
%39:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %39.sub_8bit, %39.sub_8bit, implicit-def $eflags
- JNE_1 %bb.25, implicit killed $eflags
+ JCC_1 %bb.25, 5, implicit killed $eflags
JMP_1 %bb.24
bb.24:
@@ -269,7 +269,7 @@ body: |
%41:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %41.sub_8bit, %41.sub_8bit, implicit-def $eflags
- JNE_1 %bb.27, implicit killed $eflags
+ JCC_1 %bb.27, 5, implicit killed $eflags
JMP_1 %bb.26
bb.26:
@@ -281,7 +281,7 @@ body: |
%43:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %43.sub_8bit, %43.sub_8bit, implicit-def $eflags
- JNE_1 %bb.29, implicit killed $eflags
+ JCC_1 %bb.29, 5, implicit killed $eflags
JMP_1 %bb.28
bb.28:
@@ -293,7 +293,7 @@ body: |
%45:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %45.sub_8bit, %45.sub_8bit, implicit-def $eflags
- JNE_1 %bb.31, implicit killed $eflags
+ JCC_1 %bb.31, 5, implicit killed $eflags
JMP_1 %bb.30
bb.30:
@@ -305,7 +305,7 @@ body: |
%47:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %47.sub_8bit, %47.sub_8bit, implicit-def $eflags
- JNE_1 %bb.33, implicit killed $eflags
+ JCC_1 %bb.33, 5, implicit killed $eflags
JMP_1 %bb.32
bb.32:
@@ -317,7 +317,7 @@ body: |
%49:gr8 = MOV8ri 1
TEST8rr %49, %49, implicit-def $eflags
- JNE_1 %bb.37, implicit killed $eflags
+ JCC_1 %bb.37, 5, implicit killed $eflags
JMP_1 %bb.34
bb.34:
@@ -325,7 +325,7 @@ body: |
%81:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %81.sub_8bit, %81.sub_8bit, implicit-def $eflags
- JE_1 %bb.36, implicit killed $eflags
+ JCC_1 %bb.36, 4, implicit killed $eflags
bb.35:
%82:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
@@ -355,7 +355,7 @@ body: |
MOV32mr undef %54:gr32, 1, $noreg, 0, $noreg, %1
%55:gr32 = MOV32rm %12, 1, $noreg, 140, $noreg
CMP32mi8 %55, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
- JE_1 %bb.40, implicit killed $eflags
+ JCC_1 %bb.40, 4, implicit killed $eflags
JMP_1 %bb.39
bb.39:
@@ -367,7 +367,7 @@ body: |
%56:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %56.sub_8bit, %56.sub_8bit, implicit-def $eflags
- JNE_1 %bb.42, implicit killed $eflags
+ JCC_1 %bb.42, 5, implicit killed $eflags
JMP_1 %bb.41
bb.41:
@@ -375,7 +375,7 @@ body: |
%58:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %58.sub_8bit, %58.sub_8bit, implicit-def $eflags
- JNE_1 %bb.43, implicit killed $eflags
+ JCC_1 %bb.43, 5, implicit killed $eflags
JMP_1 %bb.44
bb.42:
@@ -391,7 +391,7 @@ body: |
%60:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %60.sub_8bit, %60.sub_8bit, implicit-def $eflags
- JNE_1 %bb.46, implicit killed $eflags
+ JCC_1 %bb.46, 5, implicit killed $eflags
JMP_1 %bb.45
bb.45:
@@ -403,7 +403,7 @@ body: |
%62:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %62.sub_8bit, %62.sub_8bit, implicit-def $eflags
- JNE_1 %bb.48, implicit killed $eflags
+ JCC_1 %bb.48, 5, implicit killed $eflags
JMP_1 %bb.47
bb.47:
@@ -415,7 +415,7 @@ body: |
%64:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %64.sub_8bit, %64.sub_8bit, implicit-def $eflags
- JNE_1 %bb.50, implicit killed $eflags
+ JCC_1 %bb.50, 5, implicit killed $eflags
JMP_1 %bb.49
bb.49:
@@ -427,7 +427,7 @@ body: |
%66:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %66.sub_8bit, %66.sub_8bit, implicit-def $eflags
- JNE_1 %bb.52, implicit killed $eflags
+ JCC_1 %bb.52, 5, implicit killed $eflags
JMP_1 %bb.51
bb.51:
@@ -439,7 +439,7 @@ body: |
%68:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %68.sub_8bit, %68.sub_8bit, implicit-def $eflags
- JNE_1 %bb.54, implicit killed $eflags
+ JCC_1 %bb.54, 5, implicit killed $eflags
JMP_1 %bb.53
bb.53:
@@ -451,7 +451,7 @@ body: |
%70:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %70.sub_8bit, %70.sub_8bit, implicit-def $eflags
- JNE_1 %bb.56, implicit killed $eflags
+ JCC_1 %bb.56, 5, implicit killed $eflags
JMP_1 %bb.55
bb.55:
@@ -463,7 +463,7 @@ body: |
%72:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %72.sub_8bit, %72.sub_8bit, implicit-def $eflags
- JNE_1 %bb.58, implicit killed $eflags
+ JCC_1 %bb.58, 5, implicit killed $eflags
JMP_1 %bb.57
bb.57:
@@ -474,7 +474,7 @@ body: |
successors: %bb.62(0x00000001), %bb.59(0x7fffffff)
CMP32mi8 %0, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
- JE_1 %bb.62, implicit killed $eflags
+ JCC_1 %bb.62, 4, implicit killed $eflags
JMP_1 %bb.59
bb.59:
@@ -483,7 +483,7 @@ body: |
successors: %bb.60(0x7fffffff), %bb.61(0x00000001)
CMP32ri undef %75:gr32, 95406325, implicit-def $eflags
- JB_1 %bb.61, implicit killed $eflags
+ JCC_1 %bb.61, 2, implicit killed $eflags
JMP_1 %bb.60
bb.61:
@@ -495,7 +495,7 @@ body: |
%76:gr32_abcd = MOV32r0 implicit-def dead $eflags
TEST8rr %76.sub_8bit, %76.sub_8bit, implicit-def $eflags
- JNE_1 %bb.64, implicit killed $eflags
+ JCC_1 %bb.64, 5, implicit killed $eflags
JMP_1 %bb.63
bb.63:
Modified: llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir (original)
+++ llvm/trunk/test/CodeGen/X86/shrink_wrap_dbg_value.mir Fri Apr 5 12:28:09 2019
@@ -142,7 +142,7 @@ body: |
DBG_VALUE %fixed-stack.0, 0, !16, !DIExpression(), debug-location !26
DBG_VALUE %fixed-stack.1, 0, !15, !DIExpression(), debug-location !25
CMP32rr $eax, killed $edx, implicit-def $eflags, debug-location !27
- JL_1 %bb.4, implicit killed $eflags, debug-location !29
+ JCC_1 %bb.4, 12, implicit killed $eflags, debug-location !29
JMP_1 %bb.1, debug-location !29
bb.1.for.cond.preheader:
@@ -167,7 +167,7 @@ body: |
ADJCALLSTACKUP32 4, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp, debug-location !33
$edi = INC32r killed $edi, implicit-def dead $eflags, debug-location !30
CMP32rr $edi, $esi, implicit-def $eflags, debug-location !30
- JL_1 %bb.2, implicit killed $eflags, debug-location !34
+ JCC_1 %bb.2, 12, implicit killed $eflags, debug-location !34
bb.3:
successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir (original)
+++ llvm/trunk/test/CodeGen/X86/simple-register-allocation-read-undef.mir Fri Apr 5 12:28:09 2019
@@ -3,7 +3,7 @@
name: f
body: |
bb.0:
- JB_1 %bb.2, undef implicit killed $eflags
+ JCC_1 %bb.2, 2, undef implicit killed $eflags
JMP_1 %bb.1
bb.1:
Modified: llvm/trunk/test/CodeGen/X86/switch-lower-peel-top-case.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch-lower-peel-top-case.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/switch-lower-peel-top-case.ll (original)
+++ llvm/trunk/test/CodeGen/X86/switch-lower-peel-top-case.ll Fri Apr 5 12:28:09 2019
@@ -13,32 +13,32 @@ entry:
; CHECK: successors: %[[PEELED_CASE_LABEL:.*]](0x5999999a), %[[PEELED_SWITCH_LABEL:.*]](0x26666666)
; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18568, implicit-def $eflags
-; CHECK: JE_1 %[[PEELED_CASE_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]
; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[BB1_LABEL:.*]](0x0206d3a0), %[[BB2_LABEL:.*]](0x7df92c60)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18311, implicit-def $eflags
-; CHECK: JG_1 %[[BB2_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
; CHECK: JMP_1 %[[BB1_LABEL]]
; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE2_LABEL:.*]](0x35e50d5b), %[[BB3_LABEL:.*]](0x4a1af2a5)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], -8826, implicit-def $eflags
-; CHECK: JE_1 %[[CASE2_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE2_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB3_LABEL]]
; CHECK: [[BB3_LABEL]]
; CHECK: successors: %[[CASE5_LABEL:.*]](0x45d173c8), %[[BB4_LABEL:.*]](0x3a2e8c38)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 129, implicit-def $eflags
-; CHECK: JE_1 %[[CASE5_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE5_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB4_LABEL]]
; CHECK: [[BB4_LABEL:.*]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 8, implicit-def $eflags
-; CHECK: JE_1 %[[CASE1_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE1_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]
; CHECK: [[BB2_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE3_LABEL:.*]](0x7fe44107), %[[DEFAULT_BB_LABEL]](0x001bbef9)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri %[[VAL]], 18312, implicit-def $eflags
-; CHECK: JE_1 %[[CASE3_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE3_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]
bb1:
@@ -76,37 +76,37 @@ entry:
; CHECK: %[[VAL:[0-9]+]]:gr32 = COPY $edi
; CHECK: %{{[0-9]+}}:gr32 = ADD32ri8 %{{[0-9]+}}, -85, implicit-def dead $eflags
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %{{[0-9]+}}, 2, implicit-def $eflags
-; CHECK: JB_1 %[[PEELED_CASE_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[PEELED_CASE_LABEL]], 2, implicit $eflags
; CHECK: JMP_1 %[[PEELED_SWITCH_LABEL]]
; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[BB1_LABEL:.*]](0x0088888a), %[[BB2_LABEL:.*]](0x7f777776)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 4, implicit-def $eflags
-; CHECK: JG_1 %[[BB2_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[BB2_LABEL]], 15, implicit $eflags
; CHECK: JMP_1 %[[BB1_LABEL]]
; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE4_LABEL:.*]](0x7f775a4f), %[[BB3_LABEL:.*]](0x0088a5b1)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 1, implicit-def $eflags
-; CHECK: JE_1 %[[CASE4_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE4_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB3_LABEL]]
; CHECK: [[BB3_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE1_LABEL:.*]](0x66666666), %[[DEFAULT_BB_LABEL:.*]](0x1999999a)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], -40, implicit-def $eflags
-; CHECK: JE_1 %[[CASE1_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE1_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]
; CHECK: [[BB2_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE5_LABEL:.*]](0x00000000), %[[BB4_LABEL:.*]](0x80000000)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 5, implicit-def $eflags
-; CHECK: JE_1 %[[CASE5_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE5_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB4_LABEL]]
; CHECK: [[BB4_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE6_LABEL:.*]](0x00000000), %[[BB5_LABEL:.*]](0x80000000)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 7, implicit-def $eflags
-; CHECK: JE_1 %[[CASE6_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE6_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[BB5_LABEL]]
; CHECK: [[BB5_LABEL]].{{[a-zA-Z0-9.]+}}:
; CHECK: successors: %[[CASE7_LABEL:.*]](0x00000000), %[[DEFAULT_BB_LABEL]](0x80000000)
; CHECK: %{{[0-9]+}}:gr32 = SUB32ri8 %[[VAL]], 49, implicit-def $eflags
-; CHECK: JE_1 %[[CASE7_LABEL]], implicit $eflags
+; CHECK: JCC_1 %[[CASE7_LABEL]], 4, implicit $eflags
; CHECK: JMP_1 %[[DEFAULT_BB_LABEL]]
Modified: llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir (original)
+++ llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir Fri Apr 5 12:28:09 2019
@@ -38,7 +38,7 @@ body: |
$rax = COPY $rdi
CMP64ri8 $rax, 99, implicit-def $eflags
- JA_1 %bb.4, implicit $eflags
+ JCC_1 %bb.4, 7, implicit $eflags
JMP_1 %bb.1
; CHECK: bb.1:
@@ -55,7 +55,7 @@ body: |
liveins: $rax, $rsi
CMP64ri8 $rax, 9, implicit-def $eflags
- JA_1 %bb.3, implicit $eflags
+ JCC_1 %bb.3, 7, implicit $eflags
JMP_1 %bb.2
bb.2:
Modified: llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-dup-debugloc.ll Fri Apr 5 12:28:09 2019
@@ -6,7 +6,7 @@
; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 9, column: 5, scope: !{{[0-9]+}})
; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY $rdi
; CHECK: TEST64rr [[VREG]], [[VREG]]
-; CHECK-NEXT: JE_1 {{.+}}, debug-location [[DLOC]]
+; CHECK-NEXT: JCC_1 {{.+}}, debug-location [[DLOC]]
; CHECK-NEXT: JMP_1 {{.+}}, debug-location [[DLOC]]
target triple = "x86_64-unknown-linux-gnu"
Modified: llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir (original)
+++ llvm/trunk/test/CodeGen/X86/tail-merge-after-mbp.mir Fri Apr 5 12:28:09 2019
@@ -7,25 +7,25 @@
# CHECK-NEXT: successors: %bb.3(0x30000000), %bb.4(0x50000000)
# CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg
# CHECK-NEXT: TEST64rr $rax, $rax
-# CHECK-NEXT: JE_1 %bb.3
+# CHECK-NEXT: JCC_1 %bb.3, 4
# CHECK: bb.4:
# CHECK-NEXT: successors: %bb.5(0x30000000), %bb.10(0x50000000)
# CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0
-# CHECK-NEXT: JNE_1 %bb.10
+# CHECK-NEXT: JCC_1 %bb.10, 5
# CHECK: bb.5:
# CHECK-NEXT: successors: %bb.6(0x30000000), %bb.7(0x50000000)
# CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg
# CHECK-NEXT: TEST64rr $rax, $rax
-# CHECK-NEXT: JE_1 %bb.6
+# CHECK-NEXT: JCC_1 %bb.6, 4
# CHECK: bb.7
# CHECK-NEXT: successors: %bb.8(0x71555555), %bb.10(0x0eaaaaab)
# CHECK: CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0
-# CHECK-NEXT: JNE_1 %bb.10
+# CHECK-NEXT: JCC_1 %bb.10, 5
# CHECK: bb.8:
# CHECK-NEXT: successors: %bb.9(0x04000000), %bb.7(0x7c000000)
# CHECK: $rax = MOV64rm $r14, 1, $noreg, 0, $noreg
# CHECK-NEXT: TEST64rr $rax, $rax
-# CHECK-NEXT: JNE_1 %bb.7
+# CHECK-NEXT: JCC_1 %bb.7, 5
name: foo
body: |
@@ -33,7 +33,7 @@ body: |
successors: %bb.1(0x40000000), %bb.7(0x40000000)
TEST8ri $dl, 1, implicit-def $eflags, implicit killed $edx
- JE_1 %bb.7, implicit $eflags
+ JCC_1 %bb.7, 4, implicit $eflags
bb.1:
successors: %bb.16(0x80000000)
@@ -46,7 +46,7 @@ body: |
$rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
TEST64rr $rax, $rax, implicit-def $eflags
- JNE_1 %bb.9, implicit killed $eflags
+ JCC_1 %bb.9, 5, implicit killed $eflags
bb.8:
successors: %bb.16(0x80000000)
@@ -58,14 +58,14 @@ body: |
successors: %bb.10(0x30000000), %bb.15(0x50000000)
CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8)
- JNE_1 %bb.15, implicit $eflags
+ JCC_1 %bb.15, 5, implicit $eflags
bb.10:
successors: %bb.11(0x30000000), %bb.12(0x50000000)
$rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
TEST64rr $rax, $rax, implicit-def $eflags
- JNE_1 %bb.12, implicit $eflags
+ JCC_1 %bb.12, 5, implicit $eflags
bb.11:
successors: %bb.16(0x80000000)
@@ -77,14 +77,14 @@ body: |
successors: %bb.13(0x71555555), %bb.15(0x0eaaaaab)
CMP64mi8 killed $rax, 1, $noreg, 8, $noreg, 0, implicit-def $eflags :: (load 8), (load 8)
- JNE_1 %bb.15, implicit $eflags
+ JCC_1 %bb.15, 5, implicit $eflags
bb.13:
successors: %bb.14(0x04000000), %bb.12(0x7c000000)
$rax = MOV64rm $r14, 1, $noreg, 0, $noreg :: (load 8)
TEST64rr $rax, $rax, implicit-def $eflags
- JNE_1 %bb.12, implicit $eflags
+ JCC_1 %bb.12, 5, implicit $eflags
bb.14:
successors: %bb.16(0x80000000)
Modified: llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll Fri Apr 5 12:28:09 2019
@@ -7,7 +7,7 @@
;
; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}})
; CHECK: TEST64rr{{.*}}$rsi, renamable $rsi, implicit-def $eflags
-; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]]
+; CHECK-NEXT: JCC_1{{.*}}, debug-location [[DLOC]]
target triple = "x86_64-unknown-linux-gnu"
Modified: llvm/trunk/test/CodeGen/X86/test_x86condbr_globaladdr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/test_x86condbr_globaladdr.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/test_x86condbr_globaladdr.mir (original)
+++ llvm/trunk/test/CodeGen/X86/test_x86condbr_globaladdr.mir Fri Apr 5 12:28:09 2019
@@ -18,7 +18,7 @@ body: |
%1:gr32 = COPY $edx
%2:gr32 = MOV32rm %1:gr32, 1, $noreg, 850256, $noreg
%3:gr32 = SUB32ri %2:gr32, @img2buf_normal, implicit-def $eflags
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
JMP_1 %bb.3
bb.2:
Modified: llvm/trunk/test/CodeGen/X86/undef-eflags.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/undef-eflags.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/undef-eflags.mir (original)
+++ llvm/trunk/test/CodeGen/X86/undef-eflags.mir Fri Apr 5 12:28:09 2019
@@ -7,8 +7,8 @@ name: fallundef
tracksRegLiveness: true
body: |
bb.0:
- JE_1 %bb.1, implicit undef $eflags
- ; CHECK: JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
+ ; CHECK: JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.2
bb.1:
RET 2, undef $eax
Modified: llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/update-terminator-debugloc.ll Fri Apr 5 12:28:09 2019
@@ -24,11 +24,11 @@
; CHECK-DAG: [[VREG1:%[^ ]+]]:gr64 = COPY $rsi
; CHECK-DAG: [[VREG2:%[^ ]+]]:gr64 = COPY $rdi
; CHECK: SUB64rr [[VREG2]], [[VREG1]]
-; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
+; CHECK-NEXT: JCC_1 {{.*}}, debug-location [[DLOC]]{{$}}
; CHECK: [[VREG3:%[^ ]+]]:gr64 = PHI [[VREG2]]
; CHECK: [[VREG4:%[^ ]+]]:gr64 = nuw ADD64ri8 [[VREG3]], 4
; CHECK: SUB64rr [[VREG1]], [[VREG4]]
-; CHECK-NEXT: JNE_1 {{.*}}, debug-location [[DLOC]]{{$}}
+; CHECK-NEXT: JCC_1 {{.*}}, debug-location [[DLOC]]{{$}}
; CHECK-NEXT: JMP_1 {{.*}}, debug-location [[DLOC]]{{$}}
target triple = "x86_64-unknown-linux-gnu"
Modified: llvm/trunk/test/CodeGen/X86/update-terminator.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/update-terminator.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/update-terminator.mir (original)
+++ llvm/trunk/test/CodeGen/X86/update-terminator.mir Fri Apr 5 12:28:09 2019
@@ -48,7 +48,7 @@ body: |
bb.0 (%ir-block.0):
successors: %bb.1(50), %bb.3(50)
- JNE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 2, implicit $eflags
JMP_1 %bb.3
bb.1:
successors: %bb.2(100)
@@ -56,7 +56,7 @@ body: |
CALL64pcrel32 @dummy1, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 @dummy1, csr_64, implicit $rsp, implicit-def $rsp
CALL64pcrel32 @dummy1, csr_64, implicit $rsp, implicit-def $rsp
- JNE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 5, implicit $eflags
bb.2:
successors: %bb.4(100)
Modified: llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/xor-combine-debugloc.ll Fri Apr 5 12:28:09 2019
@@ -10,7 +10,7 @@
; CHECK-DAG: [[VREG1:%[^ ]+]]:gr32 = COPY $esi
; CHECK-DAG: [[VREG2:%[^ ]+]]:gr32 = COPY $edi
; CHECK: SUB32rr [[VREG2]], [[VREG1]], implicit-def $eflags, debug-location [[DLOC1]]
-; CHECK-NEXT: JE_1{{.*}} implicit $eflags, debug-location [[DLOC2]]
+; CHECK-NEXT: JCC_1{{.*}} 4, implicit $eflags, debug-location [[DLOC2]]
; CHECK-NEXT: JMP_1{{.*}} debug-location [[DLOC2]]
target triple = "x86_64-unknown-linux-gnu"
Modified: llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir Fri Apr 5 12:28:09 2019
@@ -101,7 +101,7 @@ body: |
liveins: $rdi
CMP64mi8 $rip, 1, _, @a, _, 0, implicit-def $eflags :: (dereferenceable load 8 from @a, align 4)
- JE_1 %bb.1, implicit $eflags
+ JCC_1 %bb.1, 4, implicit $eflags
bb.2 (%ir-block.5):
liveins: $rdi
Modified: llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/kill-after-spill.mir Fri Apr 5 12:28:09 2019
@@ -283,7 +283,7 @@ body: |
$r13 = MOV64rr $rax
renamable $ecx = XOR32rr undef $ecx, undef $ecx, implicit-def dead $eflags
renamable $r13 = AND64rr killed renamable $r13, renamable $r14, implicit-def $eflags
- JE_1 %bb.9, implicit $eflags
+ JCC_1 %bb.9, 4, implicit $eflags
bb.1.if.end:
successors: %bb.2(0x30000000), %bb.3(0x50000000)
@@ -301,7 +301,7 @@ body: |
$r12 = MOV64rr $rax
$r15 = MOV64rr $r12
renamable $r15 = AND64ri8 killed renamable $r15, -123, implicit-def $eflags
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
bb.3.private.exit:
successors: %bb.9(0x30000000), %bb.4(0x50000000)
@@ -316,7 +316,7 @@ body: |
CALL64pcrel32 @func4, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
renamable $ecx = MOV32ri 1
TEST32rr killed renamable $eax, renamable $eax, implicit-def $eflags
- JE_1 %bb.9, implicit $eflags
+ JCC_1 %bb.9, 4, implicit $eflags
bb.4.if.then8:
successors: %bb.8(0x30000000), %bb.5(0x50000000)
@@ -327,21 +327,21 @@ body: |
CALL64pcrel32 @func5, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit-def $rsp, implicit-def $ssp
renamable $rax = MOV64rm killed renamable $r13, 1, $noreg, 8, $noreg :: (load 8 from %ir.13)
TEST64rr renamable $rax, renamable $rax, implicit-def $eflags
- JE_1 %bb.8, implicit $eflags
+ JCC_1 %bb.8, 4, implicit $eflags
bb.5.land.lhs.true:
successors: %bb.6(0x30000000), %bb.7(0x50000000)
liveins: $rax, $r12, $r15
CMP32mi8 renamable $r15, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.tot_perf2, align 8)
- JNE_1 %bb.7, implicit $eflags
+ JCC_1 %bb.7, 5, implicit $eflags
bb.6.lor.lhs.false:
successors: %bb.8(0x30000000), %bb.7(0x50000000)
liveins: $rax, $r12, $r15
CMP32mi8 killed renamable $r15, 1, $noreg, 4, $noreg, 0, implicit-def $eflags :: (load 4 from %ir.tot_bw)
- JE_1 %bb.8, implicit $eflags
+ JCC_1 %bb.8, 4, implicit $eflags
bb.7.if.then14:
successors: %bb.8(0x80000000)
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir Fri Apr 5 12:28:09 2019
@@ -194,7 +194,7 @@ body: |
$r8d = MOV32rr $esi, debug-location !26
$r8d = IMUL32rr killed $r8d, $edi, implicit-def dead $eflags, debug-location !26
TEST32rr $r8d, $r8d, implicit-def $eflags, debug-location !31
- JLE_1 %bb.9.for.end, implicit $eflags
+ JCC_1 %bb.9.for.end, 14, implicit $eflags
bb.1.for.body.preheader:
successors: %bb.3.for.body(0)
@@ -217,7 +217,7 @@ body: |
DBG_VALUE $ecx, _, !12, !17, debug-location !23
DBG_VALUE 0, 0, !13, !17, debug-location !25
TEST32rr $edi, $edi, implicit-def $eflags, debug-location !35
- JG_1 %bb.4.if.then, implicit $eflags
+ JCC_1 %bb.4.if.then, 15, implicit $eflags
bb.5.if.end:
successors: %bb.6.if.then.4(4), %bb.7.if.end.6(124)
@@ -229,7 +229,7 @@ body: |
DBG_VALUE $ecx, _, !12, !17, debug-location !23
DBG_VALUE 0, 0, !13, !17, debug-location !25
TEST32rr $esi, $esi, implicit-def $eflags, debug-location !39
- JG_1 %bb.6.if.then.4, implicit $eflags
+ JCC_1 %bb.6.if.then.4, 15, implicit $eflags
bb.7.if.end.6:
successors: %bb.8.if.then.8(4), %bb.2.for.cond(124)
@@ -241,7 +241,7 @@ body: |
DBG_VALUE $ecx, _, !12, !17, debug-location !23
DBG_VALUE 0, 0, !13, !17, debug-location !25
TEST32rr $edx, $edx, implicit-def $eflags, debug-location !45
- JG_1 %bb.8.if.then.8, implicit $eflags
+ JCC_1 %bb.8.if.then.8, 15, implicit $eflags
bb.2.for.cond:
successors: %bb.3.for.body(124), %bb.9.for.end(4)
@@ -255,7 +255,7 @@ body: |
$eax = INC32r killed $eax, implicit-def dead $eflags, debug-location !44
DBG_VALUE $eax, _, !13, !17, debug-location !25
CMP32rr $eax, $r8d, implicit-def $eflags, debug-location !31
- JL_1 %bb.3.for.body, implicit $eflags
+ JCC_1 %bb.3.for.body, 12, implicit $eflags
JMP_1 %bb.9.for.end
bb.4.if.then:
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir Fri Apr 5 12:28:09 2019
@@ -159,7 +159,7 @@ body: |
$ebp = MOV32rr $eax, debug-location !15
$edi = MOV32rr $ebx, debug-location !15
CMP32ri8 renamable $ebp, 33, implicit-def $eflags, debug-location !15
- JL_1 %bb.2, implicit killed $eflags, debug-location !15
+ JCC_1 %bb.2, 12, implicit killed $eflags, debug-location !15
bb.1.if.then:
successors: %bb.3(0x80000000)
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-restore.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-restore.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-restore.mir Fri Apr 5 12:28:09 2019
@@ -140,7 +140,7 @@ body: |
DBG_VALUE $rdi, $noreg, !13, !DIExpression(), debug-location !14
DBG_VALUE $rdi, $noreg, !13, !DIExpression(), debug-location !14
TEST64rr renamable $rdi, renamable $rdi, implicit-def $eflags, debug-location !15
- JE_1 %bb.2, implicit $eflags, debug-location !17
+ JCC_1 %bb.2, 4, implicit $eflags, debug-location !17
bb.1.if.then:
successors: %bb.2(0x80000000)
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-spill.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-spill.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-spill.mir Fri Apr 5 12:28:09 2019
@@ -396,7 +396,7 @@ body: |
DBG_VALUE $edi, _, !36, !38, debug-location !63
MOV32mr $rbp, 1, _, -60, _, $edi, debug-location !63 :: (store 4 into %ir.intf, !tbaa !47)
TEST32rr killed $eax, $eax, implicit-def $eflags, debug-location !67
- JNE_1 %bb.5.cleanup, implicit $eflags
+ JCC_1 %bb.5.cleanup, 5, implicit $eflags
bb.1.if.end:
successors: %bb.2(0x30000000), %bb.3.if.then4(0x50000000)
@@ -414,7 +414,7 @@ body: |
$edi = MOV32rr killed $ebx, debug-location !73
CALL64pcrel32 @use, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !73
TEST32rr killed $r12d, $r12d, implicit-def $eflags, debug-location !74
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
bb.3.if.then4:
successors: %bb.4.if.end13(0x80000000)
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Fri Apr 5 12:28:09 2019
@@ -199,7 +199,7 @@ body: |
DBG_VALUE $eax, _, !12, !20, debug-location !21
$edi = MOV32ri 2
CMP32ri8 killed $eax, 2, implicit-def $eflags, debug-location !26
- JNE_1 %bb.2.if.end, implicit $eflags
+ JCC_1 %bb.2.if.end, 5, implicit $eflags
bb.1.if.else:
successors: %bb.2.if.end(0)
@@ -220,7 +220,7 @@ body: |
$ebx = MOV32rr $eax, debug-location !34
DBG_VALUE $ebx, _, !14, !20, debug-location !33
CMP32ri8 $ebx, 11, implicit-def $eflags, debug-location !37
- JL_1 %bb.4.if.else.5, implicit killed $eflags, debug-location !37
+ JCC_1 %bb.4.if.else.5, 12, implicit killed $eflags, debug-location !37
bb.3.if.then.3:
successors: %bb.5.if.end.7(0)
Modified: llvm/trunk/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir Fri Apr 5 12:28:09 2019
@@ -214,7 +214,7 @@ body: |
DBG_VALUE $ebx, _, !19, !13, debug-location !20
CALL64pcrel32 @sink, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, debug-location !23
TEST32rr $ebx, $ebx, implicit-def $eflags, debug-location !24
- JE_1 %bb.2.if.end, implicit $eflags
+ JCC_1 %bb.2.if.end, 4, implicit $eflags
bb.1.if.then:
successors: %bb.2.if.end
Modified: llvm/trunk/test/DebugInfo/X86/debug-loc-asan.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/debug-loc-asan.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/debug-loc-asan.mir (original)
+++ llvm/trunk/test/DebugInfo/X86/debug-loc-asan.mir Fri Apr 5 12:28:09 2019
@@ -226,7 +226,7 @@ body: |
MOV32mr $rsp, 1, $noreg, 60, $noreg, killed $edi :: (store 4 into %stack.1)
MOV64mr $rsp, 1, $noreg, 48, $noreg, killed $rax :: (store 8 into %stack.2)
MOV64mr $rsp, 1, $noreg, 40, $noreg, killed $rcx :: (store 8 into %stack.3)
- JE_1 %bb.2, implicit $eflags
+ JCC_1 %bb.2, 4, implicit $eflags
bb.1 (%ir-block.3):
$edi = MOV32ri 64, implicit-def $rdi
@@ -259,7 +259,7 @@ body: |
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
MOV64mr $rsp, 1, $noreg, 16, $noreg, killed $rsi :: (store 8 into %stack.6)
MOV8mr $rsp, 1, $noreg, 15, $noreg, killed $r8b :: (store 1 into %stack.7)
- JE_1 %bb.5, implicit $eflags
+ JCC_1 %bb.5, 4, implicit $eflags
bb.3 (%ir-block.24):
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
@@ -269,7 +269,7 @@ body: |
$cl = MOV8rr $al, implicit killed $rax
$dl = MOV8rm $rsp, 1, $noreg, 15, $noreg :: (load 1 from %stack.7)
CMP8rr killed renamable $cl, killed renamable $dl, implicit-def $eflags
- JL_1 %bb.5, implicit $eflags
+ JCC_1 %bb.5, 12, implicit $eflags
bb.4 (%ir-block.29):
successors:
@@ -288,7 +288,7 @@ body: |
renamable $dl = MOV8rm killed renamable $rax, 1, $noreg, 2147450880, $noreg, debug-location !12 :: (load 1 from %ir.34)
CMP8ri renamable $dl, 0, implicit-def $eflags, debug-location !12
MOV8mr $rsp, 1, $noreg, 14, $noreg, killed $dl :: (store 1 into %stack.8)
- JE_1 %bb.8, implicit $eflags, debug-location !12
+ JCC_1 %bb.8, 4, implicit $eflags, debug-location !12
bb.6 (%ir-block.37):
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
@@ -298,7 +298,7 @@ body: |
$cl = MOV8rr $al, implicit killed $rax, debug-location !12
$dl = MOV8rm $rsp, 1, $noreg, 14, $noreg :: (load 1 from %stack.8)
CMP8rr killed renamable $cl, killed renamable $dl, implicit-def $eflags, debug-location !12
- JL_1 %bb.8, implicit $eflags
+ JCC_1 %bb.8, 12, implicit $eflags
bb.7 (%ir-block.42):
successors:
@@ -318,7 +318,7 @@ body: |
$rsi = MOV64rm $rsp, 1, $noreg, 48, $noreg :: (load 8 from %stack.2)
CMP64rr killed renamable $rdx, killed renamable $rsi, implicit-def $eflags, debug-location !12
MOV32mr $rsp, 1, $noreg, 8, $noreg, killed $ecx :: (store 4 into %stack.9)
- JE_1 %bb.10, implicit $eflags, debug-location !12
+ JCC_1 %bb.10, 4, implicit $eflags, debug-location !12
bb.9 (%ir-block.46):
DBG_VALUE $rsp, 0, !10, !DIExpression(DW_OP_plus_uconst, 24, DW_OP_deref, DW_OP_deref), debug-location !11
Modified: llvm/trunk/test/DebugInfo/X86/debug-loc-offset.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/debug-loc-offset.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/debug-loc-offset.mir (original)
+++ llvm/trunk/test/DebugInfo/X86/debug-loc-offset.mir Fri Apr 5 12:28:09 2019
@@ -243,7 +243,7 @@ body: |
CMP32mi8 renamable $eax, 1, $noreg, 4, $noreg, 2, implicit-def $eflags, debug-location !24 :: (load 4 from %ir.var)
MOV32mr $ebp, 1, $noreg, -8, $noreg, killed $eax :: (store 4 into %stack.1)
DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
- JLE_1 %bb.2, implicit $eflags, debug-location !24
+ JCC_1 %bb.2, 14, implicit $eflags, debug-location !24
bb.1.if.then:
DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
@@ -258,7 +258,7 @@ body: |
CALLpcrel32 @_ZN1A3fooEv, csr_32, implicit $esp, implicit $ssp, implicit-def $al, debug-location !27
renamable $ecx = MOVSX32rr8 killed renamable $al, debug-location !27
CMP32ri8 killed renamable $ecx, 97, implicit-def $eflags, debug-location !27
- JNE_1 %bb.4, implicit $eflags, debug-location !27
+ JCC_1 %bb.4, 5, implicit $eflags, debug-location !27
bb.3.if.then2:
DBG_VALUE $ebp, 0, !20, !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !21
Modified: llvm/trunk/test/DebugInfo/X86/pr19307.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/pr19307.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/pr19307.mir (original)
+++ llvm/trunk/test/DebugInfo/X86/pr19307.mir Fri Apr 5 12:28:09 2019
@@ -191,7 +191,7 @@ body: |
renamable $rcx = MOV64ri @.str, debug-location !46
CALL64pcrel32 @_ZNKSs7compareEmmPKc, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit killed $rdx, implicit killed $rcx, implicit-def $eax, debug-location !46
CMP32ri8 killed renamable $eax, 0, implicit-def $eflags, debug-location !46
- JNE_1 %bb.2, implicit $eflags, debug-location !46
+ JCC_1 %bb.2, 5, implicit $eflags, debug-location !46
bb.1.lor.lhs.false:
DBG_VALUE $rbp, 0, !44, !DIExpression(DW_OP_constu, 24, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !45
@@ -200,7 +200,7 @@ body: |
CALL64pcrel32 @_ZNSsixEm, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit killed $rsi, implicit-def $rax, debug-location !48
renamable $ecx = MOVSX32rm8 killed renamable $rax, 1, $noreg, 0, $noreg, debug-location !48 :: (load 1 from %ir.call1)
CMP32ri8 killed renamable $ecx, 45, implicit-def $eflags, debug-location !48
- JNE_1 %bb.3, implicit $eflags, debug-location !48
+ JCC_1 %bb.3, 5, implicit $eflags, debug-location !48
bb.2.if.then:
DBG_VALUE $rbp, 0, !44, !DIExpression(DW_OP_constu, 24, DW_OP_minus, DW_OP_deref, DW_OP_deref), debug-location !45
Modified: llvm/trunk/test/MachineVerifier/verifier-phi-fail0.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MachineVerifier/verifier-phi-fail0.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/MachineVerifier/verifier-phi-fail0.mir (original)
+++ llvm/trunk/test/MachineVerifier/verifier-phi-fail0.mir Fri Apr 5 12:28:09 2019
@@ -17,7 +17,7 @@ name: func0
tracksRegLiveness: true
body: |
bb.0:
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.2
bb.1:
Modified: llvm/trunk/test/MachineVerifier/verifier-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MachineVerifier/verifier-phi.mir?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/test/MachineVerifier/verifier-phi.mir (original)
+++ llvm/trunk/test/MachineVerifier/verifier-phi.mir Fri Apr 5 12:28:09 2019
@@ -9,7 +9,7 @@ name: func0
tracksRegLiveness: true
body: |
bb.0:
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.2
bb.1:
@@ -25,7 +25,7 @@ tracksRegLiveness: true
body: |
bb.0:
%0 : gr32 = IMPLICIT_DEF
- JE_1 %bb.1, implicit undef $eflags
+ JCC_1 %bb.1, 4, implicit undef $eflags
JMP_1 %bb.2
bb.1:
Modified: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp Fri Apr 5 12:28:09 2019
@@ -28,6 +28,7 @@ static Error isInvalidMemoryInstr(const
// These have no memory access.
case X86II::Pseudo:
case X86II::RawFrm:
+ case X86II::AddCCFrm:
case X86II::MRMDestReg:
case X86II::MRMSrcReg:
case X86II::MRMSrcReg4VOp3:
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Fri Apr 5 12:28:09 2019
@@ -495,6 +495,13 @@ void RecognizableInstr::emitInstructionS
HANDLE_OPERAND(opcodeModifier)
HANDLE_OPTIONAL(relocation)
break;
+ case X86Local::AddCCFrm:
+ // Operand 1 (optional) is an address or immediate.
+ assert(numPhysicalOperands == 2 &&
+ "Unexpected number of operands for AddCCFrm");
+ HANDLE_OPERAND(relocation)
+ HANDLE_OPERAND(opcodeModifier)
+ break;
case X86Local::MRMDestReg:
// Operand 1 is a register operand in the R/M field.
// - In AVX512 there may be a mask operand here -
@@ -749,6 +756,7 @@ void RecognizableInstr::emitDecodePath(D
case X86Local::RawFrmDstSrc:
case X86Local::RawFrmImm8:
case X86Local::RawFrmImm16:
+ case X86Local::AddCCFrm:
filter = llvm::make_unique<DumbFilter>();
break;
case X86Local::MRMDestReg:
@@ -800,7 +808,7 @@ void RecognizableInstr::emitDecodePath(D
if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
- Form == X86Local::MRMXmCC) {
+ Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) {
unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16;
assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.h?rev=357802&r1=357801&r2=357802&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.h (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.h Fri Apr 5 12:28:09 2019
@@ -101,6 +101,7 @@ namespace X86Local {
RawFrmDstSrc = 6,
RawFrmImm8 = 7,
RawFrmImm16 = 8,
+ AddCCFrm = 9,
MRMDestMem = 32,
MRMSrcMem = 33,
MRMSrcMem4VOp3 = 34,
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