[PATCH] D60286: [x86] make 8-bit shl undesirable

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, lebedev.ri, andreadb.
Herald added subscribers: javed.absar, hiraditya, mcrosier.
Herald added a project: LLVM.

I was looking at a potential DAGCombiner fix for 1 of the regressions in D60278 <https://reviews.llvm.org/D60278>, and it caused severe regression test pain because x86 TLI lies about the desirability of 8-bit shift ops.

We've hinted at making all 8-bit ops undesirable for the reason in the code comment:

  // TODO: Almost no 8-bit ops are desirable because they have no actual
  //       size/speed advantages vs. 32-bit ops, but they do have a major
  //       potential disadvantage by causing partial register stalls.

...but that leads to massive diffs and exposes all kinds of optimization holes itself. So I'm trying for 1 tiny opcode step at a time. :)


https://reviews.llvm.org/D60286

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/bt.ll
  llvm/test/CodeGen/X86/btc_bts_btr.ll
  llvm/test/CodeGen/X86/rotate4.ll
  llvm/test/CodeGen/X86/scheduler-backtracking.ll
  llvm/test/CodeGen/X86/select_const.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D60286.193786.patch
Type: text/x-patch
Size: 8285 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190404/ba5cf117/attachment.bin>