[PATCH] D60228: [X86] Merge the different Jcc instructions for each condition code into single instructions that store the condition code as an operand.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 3 12:50:47 PDT 2019 

craig.topper created this revision.
craig.topper added reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon.
Herald added subscribers: arphaman, hiraditya, eraman, qcolombet, MatzeB.
Herald added a project: LLVM.
craig.topper added a parent revision: D60138: [X86] Merge the different SETcc instructions for each condition code into single instructions that store the condition code as an operand..

This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes.

Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser.


https://reviews.llvm.org/D60228

Files:
  llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/X86CmovConversion.cpp
  llvm/lib/Target/X86/X86CondBrFolding.cpp
  llvm/lib/Target/X86/X86ExpandPseudo.cpp
  llvm/lib/Target/X86/X86FastISel.cpp
  llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86InstrControl.td
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/lib/Target/X86/X86InstructionSelector.cpp
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86MacroFusion.cpp
  llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
  llvm/test/CodeGen/MIR/X86/auto-successor.mir
  llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
  llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
  llvm/test/CodeGen/MIR/X86/branch-probabilities.mir
  llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
  llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
  llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
  llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
  llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
  llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
  llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
  llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
  llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
  llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
  llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
  llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
  llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
  llvm/test/CodeGen/MIR/X86/jump-table-info.mir
  llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir
  llvm/test/CodeGen/MIR/X86/killed-register-flag.mir
  llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
  llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
  llvm/test/CodeGen/MIR/X86/memory-operands.mir
  llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
  llvm/test/CodeGen/MIR/X86/newline-handling.mir
  llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir
  llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir
  llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir
  llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
  llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
  llvm/test/CodeGen/MIR/X86/virtual-registers.mir
  llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir
  llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
  llvm/test/CodeGen/X86/PR37310.mir
  llvm/test/CodeGen/X86/block-placement.mir
  llvm/test/CodeGen/X86/branchfolding-undef.mir
  llvm/test/CodeGen/X86/cfi-inserter-cfg-with-merge.mir
  llvm/test/CodeGen/X86/cfi-inserter-noreturnblock.mir
  llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir
  llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir
  llvm/test/CodeGen/X86/cmovcmov.ll
  llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir
  llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir
  llvm/test/CodeGen/X86/debugloc-no-line-0.ll
  llvm/test/CodeGen/X86/domain-reassignment.mir
  llvm/test/CodeGen/X86/fixup-bw-inst.mir
  llvm/test/CodeGen/X86/flags-copy-lowering.mir
  llvm/test/CodeGen/X86/implicit-null-checks.mir
  llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir
  llvm/test/CodeGen/X86/invalid-liveness.mir
  llvm/test/CodeGen/X86/late-remat-update-2.mir
  llvm/test/CodeGen/X86/late-remat-update.mir
  llvm/test/CodeGen/X86/leaFixup32.mir
  llvm/test/CodeGen/X86/leaFixup64.mir
  llvm/test/CodeGen/X86/limit-split-cost.mir
  llvm/test/CodeGen/X86/machine-region-info.mir
  llvm/test/CodeGen/X86/non-value-mem-operand.mir
  llvm/test/CodeGen/X86/opt_phis2.mir
  llvm/test/CodeGen/X86/peephole-recurrence.mir
  llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
  llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir
  llvm/test/CodeGen/X86/pr27681.mir
  llvm/test/CodeGen/X86/pr38952.mir
  llvm/test/CodeGen/X86/pre-coalesce.mir
  llvm/test/CodeGen/X86/regalloc-copy-hints.mir
  llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir
  llvm/test/CodeGen/X86/simple-register-allocation-read-undef.mir
  llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll
  llvm/test/CodeGen/X86/tail-call-conditional.mir
  llvm/test/CodeGen/X86/tail-dup-debugloc.ll
  llvm/test/CodeGen/X86/tail-merge-after-mbp.mir
  llvm/test/CodeGen/X86/tail-merge-debugloc.ll
  llvm/test/CodeGen/X86/test_x86condbr_globaladdr.mir
  llvm/test/CodeGen/X86/undef-eflags.mir
  llvm/test/CodeGen/X86/update-terminator-debugloc.ll
  llvm/test/CodeGen/X86/update-terminator.mir
  llvm/test/CodeGen/X86/xor-combine-debugloc.ll
  llvm/test/DebugInfo/MIR/X86/empty-inline.mir
  llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
  llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
  llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
  llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
  llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
  llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
  llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
  llvm/test/DebugInfo/X86/debug-loc-asan.mir
  llvm/test/DebugInfo/X86/debug-loc-offset.mir
  llvm/test/DebugInfo/X86/pr19307.mir
  llvm/test/MachineVerifier/verifier-phi-fail0.mir
  llvm/test/MachineVerifier/verifier-phi.mir
  llvm/tools/llvm-exegesis/lib/X86/Target.cpp
  llvm/utils/TableGen/X86RecognizableInstr.cpp
  llvm/utils/TableGen/X86RecognizableInstr.h

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