[PATCH] D55303: [RISCV] Add lowering of addressing sequences for PIC
James Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 3 07:31:07 PDT 2019
jrtc27 added a comment.
Herald added subscribers: benna, psnobl.
Herald added a project: LLVM.
One minor comment, but otherwise I think this is ready to land now?
================
Comment at: lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:616
+ if (!MF->getTarget().isPositionIndependent())
+ return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
+ RISCV::ADDI);
----------------
rogfer01 wrote:
> Perhaps it is clearer if we call `expandLoadLocalAddress` here instead of repeating the call to `expandAuipcInstPair`.
I think it's better to match RISCVAsmParser::emitLoadAddress, which would make this something like:
```lang=C++
unsigned SecondOpcode;
unsigned FlagsHi;
if (MF->getTarget().isPositionIndependent()) {
const auto &STI = MF->getSubtarget<RISCVSubtarget>();
SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
FlagsHi = RISCVII::MO_GOT_HI;
} else {
SecondOpcode = RISCV::ADDI;
FlagsHi = RISCVII::MO_PCREL_HI,
}
return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi,
SecondOpcode);
```
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D55303/new/
https://reviews.llvm.org/D55303
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