[PATCH] D60146: AMDGPU: Don't use generation to determine encoding

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: kzhuravl, rampitec, scott.linder.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely.

There's already a dedicated feature for this.


https://reviews.llvm.org/D60146

Files:
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/SIInstrInfo.cpp
  test/CodeGen/AMDGPU/gcn3-encoding-feature.ll


Index: test/CodeGen/AMDGPU/gcn3-encoding-feature.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/gcn3-encoding-feature.ll
@@ -0,0 +1,26 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -show-mc-encoding < %s | FileCheck %s
+
+; CHECK-LABEL: func_vi:
+; CHECK: v_add_f32_e32 v0, 1.0, v0 ; encoding: [0xf2,0x00,0x00,0x02]
+define float @func_vi(float %arg0) #1 {
+  %fadd = fadd float %arg0, 1.0
+  ret float %fadd
+}
+
+; CHECK-LABEL: func_si:
+; CHECK: v_add_f32_e32 v0, 1.0, v0 ; encoding: [0xf2,0x00,0x00,0x06]
+define float @func_si(float %arg0) #0 {
+  %fadd = fadd float %arg0, 1.0
+  ret float %fadd
+}
+
+; Defaults to SI encoding
+; CHECK-LABEL: func_unknown:
+; CHECK: v_add_f32_e32 v0, 1.0, v0 ; encoding: [0xf2,0x00,0x00,0x06]
+define float @func_unknown(float %arg0) {
+  %fadd = fadd float %arg0, 1.0
+  ret float %fadd
+}
+
+attributes #0 = { "target-features"="-gcn3-encoding" }
+attributes #1 = { "target-features"="+gcn3-encoding" }
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5587,22 +5587,9 @@
   GFX9 = 5
 };
 
-static SIEncodingFamily subtargetEncodingFamily(const GCNSubtarget &ST) {
-  switch (ST.getGeneration()) {
-  default:
-    break;
-  case AMDGPUSubtarget::SOUTHERN_ISLANDS:
-  case AMDGPUSubtarget::SEA_ISLANDS:
-    return SIEncodingFamily::SI;
-  case AMDGPUSubtarget::VOLCANIC_ISLANDS:
-  case AMDGPUSubtarget::GFX9:
-    return SIEncodingFamily::VI;
-  }
-  llvm_unreachable("Unknown subtarget generation!");
-}
-
 int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
-  SIEncodingFamily Gen = subtargetEncodingFamily(ST);
+  SIEncodingFamily Gen
+    = ST.isGCN3Encoding() ? SIEncodingFamily::VI : SIEncodingFamily::SI;
 
   if ((get(Opcode).TSFlags & SIInstrFlags::renamedInGFX9) != 0 &&
     ST.getGeneration() >= AMDGPUSubtarget::GFX9)
Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -411,6 +411,10 @@
     return (Generation)Gen;
   }
 
+  bool isGCN3Encoding() const {
+    return GCN3Encoding;
+  }
+
   unsigned getWavefrontSizeLog2() const {
     return Log2_32(WavefrontSize);
   }


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