[llvm] r357472 - [mips] Use AltOrders to prevent using odd FP-registers
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 2 06:57:32 PDT 2019
Author: atanasyan
Date: Tue Apr 2 06:57:32 2019
New Revision: 357472
URL: http://llvm.org/viewvc/llvm-project?rev=357472&view=rev
Log:
[mips] Use AltOrders to prevent using odd FP-registers
To disable using of odd floating-point registers (O32 ABI and
-mno-odd-spreg command line option) such registers and their
super-registers added to the set of reserved registers. In general, it
works. But there is at least one problem - in case of enabled machine
verifier pass some floating-point tests failed because live ranges of
register units that are reserved is not empty and verification pass
failed with "Live segment doesn't end at a valid instruction" error
message.
There is D35985 patch which tries to solve the problem by explicit
removing of register units. This solution did not get approval.
I would like to use another approach for prevent using odd floating
point registers - define `AltOrders` and `AltOrderSelect` for MIPS
floating point register classes. Such `AltOrders` contains reduced set
of registers. At first glance, such solution does not break any test
cases and allows enabling machine instruction verification for all MIPS
test cases.
Differential Revision: http://reviews.llvm.org/D59799
Modified:
llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp?rev=357472&r1=357471&r2=357472&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp Tue Apr 2 06:57:32 2019
@@ -83,7 +83,6 @@ const RegisterBank &MipsRegisterBankInfo
case Mips::FGRCCRegClassID:
case Mips::FGR64RegClassID:
case Mips::AFGR64RegClassID:
- case Mips::AFGR64_and_OddSPRegClassID:
return getRegBank(Mips::FPRBRegBankID);
default:
llvm_unreachable("Register class not supported");
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=357472&r1=357471&r2=357472&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Apr 2 06:57:32 2019
@@ -247,11 +247,6 @@ getReservedRegs(const MachineFunction &M
Reserved.set(Mips::GP_64);
}
- if (Subtarget.isABI_O32() && !Subtarget.useOddSPReg()) {
- for (const auto &Reg : Mips::OddSPRegClass)
- Reserved.set(Reg);
- }
-
return Reserved;
}
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=357472&r1=357471&r2=357472&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Tue Apr 2 06:57:32 2019
@@ -382,10 +382,24 @@ def CPUSPReg : RegisterClass<"Mips", [i3
// 32bit fp:
// * FGR32 - 16 32-bit even registers
// * FGR32 - 32 32-bit registers (single float only mode)
-def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
+def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> {
+ // Do not allocate odd registers when given -mattr=+nooddspreg.
+ let AltOrders = [(decimate FGR32, 2)];
+ let AltOrderSelect = [{
+ const auto & S = MF.getSubtarget<MipsSubtarget>();
+ return S.isABI_O32() && !S.useOddSPReg();
+ }];
+}
def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
- Unallocatable;
+ Unallocatable {
+ // Do not allocate odd registers when given -mattr=+nooddspreg.
+ let AltOrders = [(decimate FGRH32, 2)];
+ let AltOrderSelect = [{
+ const auto & S = MF.getSubtarget<MipsSubtarget>();
+ return S.isABI_O32() && !S.useOddSPReg();
+ }];
+}
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments
@@ -399,16 +413,14 @@ def AFGR64 : RegisterClass<"Mips", [f64]
// Callee save
D10, D11, D12, D13, D14, D15)>;
-def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
-
-// Used to reserve odd registers when given -mattr=+nooddspreg
-// FIXME: Remove double precision registers from this set.
-def OddSP : RegisterClass<"Mips", [f32], 32,
- (add (decimate (sequence "F%u", 1, 31), 2),
- (decimate (sequence "F_HI%u", 1, 31), 2),
- (decimate (sequence "D%u", 1, 15), 2),
- (decimate (sequence "D%u_64", 1, 31), 2))>,
- Unallocatable;
+def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> {
+ // Do not allocate odd registers when given -mattr=+nooddspreg.
+ let AltOrders = [(decimate FGR64, 2)];
+ let AltOrderSelect = [{
+ const auto & S = MF.getSubtarget<MipsSubtarget>();
+ return S.isABI_O32() && !S.useOddSPReg();
+ }];
+}
// FP control registers.
def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
Modified: llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll?rev=357472&r1=357471&r2=357472&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/no-odd-spreg-msa.ll Tue Apr 2 06:57:32 2019
@@ -1,8 +1,8 @@
; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,-nooddspreg \
-; RUN: -no-integrated-as -relocation-model=pic < %s | \
+; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,ODDSPREG
; RUN: llc -march=mipsel -mcpu=mips32r5 -mattr=+fp64,+msa,+nooddspreg \
-; RUN: -no-integrated-as -relocation-model=pic < %s | \
+; RUN: -verify-machineinstrs -no-integrated-as -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,NOODDSPREG
@v4f32 = global <4 x float> zeroinitializer
@@ -31,9 +31,9 @@ entry:
; ALL-LABEL: msa_insert_0:
; ALL: mov.s $f13, $f12
+; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
-; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
; ALL: teqi $zero, 1
@@ -65,9 +65,9 @@ entry:
; ALL-LABEL: msa_insert_1:
; ALL: mov.s $f13, $f12
+; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
-; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
; ALL: teqi $zero, 1
More information about the llvm-commits
mailing list