[PATCH] D60109: AMDGPU: Split block for si_end_cf

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, nhaehnle.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.

Relying on no spill or other code being inserted before this was
precarious. It relied on code diligently checking isBasicBlockPrologue
which is likely to be forgotten.

      

Ideally this could be done earlier, but this doesn't work because of
phis. Any other instruction can't be placed before them, so we have to
accept the position being incorrect during SSA.

      

This avoids regressions in the fast register allocator rewrite from
inverting the direction.


https://reviews.llvm.org/D60109

Files:
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SILowerControlFlow.cpp
  lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  test/CodeGen/AMDGPU/collapse-endcf.mir
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll

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