[llvm] r357442 - [AMDGPU] Add more test cases of D59608.
Michael Liao via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 1 17:36:37 PDT 2019
Author: hliao
Date: Mon Apr 1 17:36:37 2019
New Revision: 357442
URL: http://llvm.org/viewvc/llvm-project?rev=357442&view=rev
Log:
[AMDGPU] Add more test cases of D59608.
Summary: - Add more test cases.
Reviewers: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60071
Modified:
llvm/trunk/test/CodeGen/AMDGPU/ds-sub-offset.ll
llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll
llvm/trunk/test/CodeGen/AMDGPU/usubo.ll
Modified: llvm/trunk/test/CodeGen/AMDGPU/ds-sub-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ds-sub-offset.ll?rev=357442&r1=357441&r2=357442&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ds-sub-offset.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/ds-sub-offset.ll Mon Apr 1 17:36:37 2019
@@ -21,6 +21,21 @@ entry:
ret void
}
+; GFX9-LABEL: {{^}}write_ds_sub0_offset0_global_clamp_bit:
+; GFX9: v_sub_u32
+; GFX9: s_endpgm
+define amdgpu_kernel void @write_ds_sub0_offset0_global_clamp_bit(float %dummy.val) #0 {
+entry:
+ %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %sub1 = sub i32 0, %x.i
+ %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
+ %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
+ store i32 123, i32 addrspace(3)* %arrayidx
+ %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
+ store volatile float %fmas, float addrspace(1)* null
+ ret void
+}
+
; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
@@ -112,6 +127,21 @@ define amdgpu_kernel void @add_x_shl_neg
ret void
}
+; GFX9-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:
+; GFX9: v_sub_u32
+; GFX9: s_endpgm
+define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit(float %dummy.val) #1 {
+ %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
+ %neg = sub i32 0, %x.i
+ %shl = shl i32 %neg, 2
+ %add = add i32 1019, %shl
+ %ptr = inttoptr i32 %add to i64 addrspace(3)*
+ store i64 123, i64 addrspace(3)* %ptr, align 4
+ %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
+ store volatile float %fmas, float addrspace(1)* null
+ ret void
+}
+
; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
@@ -127,6 +157,8 @@ define amdgpu_kernel void @add_x_shl_neg
ret void
}
+declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1)
+
attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }
attributes #2 = { nounwind convergent }
Modified: llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll?rev=357442&r1=357441&r2=357442&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/uaddo.ll Mon Apr 1 17:36:37 2019
@@ -192,6 +192,33 @@ exit:
ret void
}
+; FUNC-LABEL: {{^}}v_uaddo_clamp_bit:
+; GCN: v_add_{{i|u|co_u}}32_e64
+; GCN: s_endpgm
+define amdgpu_kernel void @v_uaddo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
+entry:
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
+ %b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
+ %a = load i32, i32 addrspace(1)* %a.gep
+ %b = load i32, i32 addrspace(1)* %b.gep
+ %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
+ %val = extractvalue { i32, i1 } %uadd, 0
+ %carry = extractvalue { i32, i1 } %uadd, 1
+ %c2 = icmp eq i1 %carry, false
+ %cc = icmp eq i32 %a, %b
+ br i1 %cc, label %exit, label %if
+
+if:
+ br label %exit
+
+exit:
+ %cout = phi i1 [false, %entry], [%c2, %if]
+ store i32 %val, i32 addrspace(1)* %out, align 4
+ store i1 %cout, i1 addrspace(1)* %carryout
+ ret void
+}
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
Modified: llvm/trunk/test/CodeGen/AMDGPU/usubo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/usubo.ll?rev=357442&r1=357441&r2=357442&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/usubo.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/usubo.ll Mon Apr 1 17:36:37 2019
@@ -176,6 +176,57 @@ define amdgpu_kernel void @v_usubo_v2i32
ret void
}
+; FUNC-LABEL: {{^}}s_usubo_clamp_bit:
+; GCN: v_sub_{{i|u|co_u}}32_e32
+; GCN: s_endpgm
+define amdgpu_kernel void @s_usubo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
+entry:
+ %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
+ %val = extractvalue { i32, i1 } %usub, 0
+ %carry = extractvalue { i32, i1 } %usub, 1
+ %c2 = icmp eq i1 %carry, false
+ %cc = icmp eq i32 %a, %b
+ br i1 %cc, label %exit, label %if
+
+if:
+ br label %exit
+
+exit:
+ %cout = phi i1 [false, %entry], [%c2, %if]
+ store i32 %val, i32 addrspace(1)* %out, align 4
+ store i1 %cout, i1 addrspace(1)* %carryout
+ ret void
+}
+
+
+; FUNC-LABEL: {{^}}v_usubo_clamp_bit:
+; GCN: v_sub_{{i|u|co_u}}32_e64
+; GCN: s_endpgm
+define amdgpu_kernel void @v_usubo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
+entry:
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %tid.ext = sext i32 %tid to i64
+ %a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
+ %b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
+ %a = load i32, i32 addrspace(1)* %a.gep, align 4
+ %b = load i32, i32 addrspace(1)* %b.gep, align 4
+ %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
+ %val = extractvalue { i32, i1 } %usub, 0
+ %carry = extractvalue { i32, i1 } %usub, 1
+ %c2 = icmp eq i1 %carry, false
+ %cc = icmp eq i32 %a, %b
+ br i1 %cc, label %exit, label %if
+
+if:
+ br label %exit
+
+exit:
+ %cout = phi i1 [false, %entry], [%c2, %if]
+ store i32 %val, i32 addrspace(1)* %out, align 4
+ store i1 %cout, i1 addrspace(1)* %carryout
+ ret void
+}
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare { i16, i1 } @llvm.usub.with.overflow.i16(i16, i16) #1
declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1
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