[PATCH] D60102: [PowerPC] Try harder to avoid load/move-to VSR for partial vector loads

[Roland Froese via Phabricator via llvm-commits]

RolandF created this revision.
RolandF added a reviewer: nemanjai.
Herald added subscribers: jsji, kbarton, hiraditya.
Herald added a project: LLVM.

There is code in the PPC code generator to avoid merging a load with an add to get an update form load if the load consumer is a single scalar to vector conversion, where we could use a partial vector load.  This code currently only looks for 64-bit int cases, and it gets confused by token factor uses.  Update the code to handle 32-bit, 16-bit, and 8-bit partial vector loads for supporting processors, and only check the register result uses.


https://reviews.llvm.org/D60102

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

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