[PATCH] D60041: [X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 193169.
craig.topper added a comment.
Herald added a subscriber: hiraditya.

Rebase after also providing a separate OperandType for AVX512 rounding control


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60041/new/

https://reviews.llvm.org/D60041

Files:
  llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
  llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
  llvm/lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp
  llvm/lib/Target/X86/InstPrinter/X86InstPrinterCommon.h
  llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
  llvm/lib/Target/X86/X86CmovConversion.cpp
  llvm/lib/Target/X86/X86FastISel.cpp
  llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86InstrCMovSetCC.td
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86InstrFoldTables.cpp
  llvm/lib/Target/X86/X86InstrFormats.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedPredicates.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/lib/Target/X86/X86Schedule.td
  llvm/lib/Target/X86/X86ScheduleAtom.td
  llvm/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/lib/Target/X86/X86ScheduleSLM.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
  llvm/test/CodeGen/X86/flags-copy-lowering.mir
  llvm/test/CodeGen/X86/non-value-mem-operand.mir
  llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
  llvm/test/CodeGen/X86/tail-call-conditional.mir
  llvm/tools/llvm-exegesis/lib/X86/Target.cpp
  llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
  llvm/utils/TableGen/X86RecognizableInstr.cpp
  llvm/utils/TableGen/X86RecognizableInstr.h

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