[PATCH] D60083: [AArch64][GlobalISe] Select STRQui for stores into v264s instead of scalarizing

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This improves selection for vector stores into v2s64s. Before we just scalarized them, but we can just use a STRQui instead.


https://reviews.llvm.org/D60083

Files:
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -29,6 +29,7 @@
   define void @store_gep_8_s32_fpr(i32* %addr) { ret void }
 
   define void @store_v2s32(i64 *%addr) { ret void }
+  define void @store_v2s64(i64 *%addr) { ret void }
 ...
 
 ---
@@ -418,3 +419,24 @@
     G_STORE  %1, %0 :: (store 8 into %ir.addr)
 
 ...
+---
+name:            store_v2s64
+legalized:       true
+regBankSelected: true
+
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: fpr }
+
+body:             |
+  bb.0:
+    liveins: $x0, $d1
+    ; CHECK-LABEL: name: store_v2s64
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
+    ; CHECK: STRQui [[COPY1]], [[COPY]], 0 :: (store 16 into %ir.addr, align 8)
+    %0(p0) = COPY $x0
+    %1(<2 x s64>) = COPY $q1
+    G_STORE %1, %0 :: (store 16 into %ir.addr, align 8)
+
+...
Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-fewerElts.mir
@@ -42,10 +42,8 @@
     ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
     ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
     ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8)
-    ; CHECK: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8, align 16)
-    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-    ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64)
-    ; CHECK: G_STORE [[LOAD1]](s64), [[GEP1]](p0) :: (store 8)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
+    ; CHECK: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY1]](p0) :: (store 16)
     %0:_(p0) = COPY $x0
     %1:_(p0) = COPY $x1
     %2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16)
Index: llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -234,7 +234,8 @@
                                  {s32, p0, 32, 8},
                                  {s64, p0, 64, 8},
                                  {p0, p0, 64, 8},
-                                 {v2s32, p0, 64, 8}})
+                                 {v2s32, p0, 64, 8},
+                                 {v2s64, p0, 128, 8}})
       .clampScalar(0, s8, s64)
       .widenScalarToNextPow2(0)
       // TODO: We could support sum-of-pow2's but the lowering code doesn't know


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