[PATCH] D59295: [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:454-458
+  const unsigned Reg = FirstDst->getReg();
+
+  const TargetRegisterClass *DstRC = TargetRegisterInfo::isVirtualRegister(Reg)
+                                         ? MRI.getRegClass(Reg)
+                                         : RI.getPhysRegClass(Reg);
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This is a separate change


================
Comment at: lib/Target/AMDGPU/SIMachineFunctionInfo.h:260
 
+  SparseBitVector<> WWMReservedRegs;
+
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This should be serialized into YAML. Maybe this should also be in terms of RegUnits?


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Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:103
+  for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) {
+    if (!MRI->isPhysRegUsed(PhysReg) &&
+        Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) {
----------------
Is the isPhysRegUsed check really necessary? It's going to break if you have multiple WWM sections


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59295/new/

https://reviews.llvm.org/D59295