[llvm] r357397 - [AArch64] Add v8.5-a Memory Tagging STZGM instruction

[David Spickett via llvm-commits]

Author: davidspickett
Date: Mon Apr  1 07:56:37 2019
New Revision: 357397

URL: http://llvm.org/viewvc/llvm-project?rev=357397&view=rev
Log:
[AArch64] Add v8.5-a Memory Tagging STZGM instruction

This instruction writes a block of allocation tags
and stores zero to the associated data locations.

It differs from STGM by 1 bit and has the same
arguments.

The specification can be found here:
https://developer.arm.com/docs/ddi0596/c

Differential Revision: https://reviews.llvm.org/D60065


Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s
    llvm/trunk/test/MC/AArch64/armv8.5a-mte.s
    llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=357397&r1=357396&r2=357397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Mon Apr  1 07:56:37 2019
@@ -1261,6 +1261,10 @@ def LDGM : MemTagVector<1, "ldgm", "\t$R
 def STGM : MemTagVector<0, "stgm", "\t$Rt, [$Rn]",
                    (outs), (ins GPR64:$Rt, GPR64sp:$Rn)>;
 
+def STZGM : MemTagVector<0, "stzgm", "\t$Rt, [$Rn]",
+                   (outs), (ins GPR64:$Rt, GPR64sp:$Rn)> {
+  let Inst{23} = 0;
+}
 
 defm STG   : MemTagStore<0b00, "stg">;
 defm STZG  : MemTagStore<0b01, "stzg">;

Modified: llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s?rev=357397&r1=357396&r2=357397&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s Mon Apr  1 07:56:37 2019
@@ -858,3 +858,26 @@ stgm x0, [#1]
 // CHECK-NEXT: stgm #1, [x1]
 // CHECK:      invalid operand for instruction
 // CHECK-NEXT: stgm x0, [#1]
+
+stzgm
+stzgm x0
+stzgm sp, [x0]
+stzgm w0, [x0]
+stzgm x0, [w0]
+stzgm #1, [x1]
+stzgm x0, [#1]
+
+// CHECK:      too few operands for instruction
+// CHECK-NEXT: stzgm
+// CHECK:      too few operands for instruction
+// CHECK-NEXT: stzgm x0
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: stzgm sp, [x0]
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: stzgm w0, [x0]
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: stzgm x0, [w0]
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: stzgm #1, [x1]
+// CHECK:      invalid operand for instruction
+// CHECK-NEXT: stzgm x0, [#1]

Modified: llvm/trunk/test/MC/AArch64/armv8.5a-mte.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-mte.s?rev=357397&r1=357396&r2=357397&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-mte.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-mte.s Mon Apr  1 07:56:37 2019
@@ -544,6 +544,7 @@ ldgm xzr, [x2]
 
 // NOMTE: instruction requires: mte
 // NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
 
 stgm x0, [x1]
 stgm x1, [sp]
@@ -555,3 +556,16 @@ stgm xzr, [x2]
 
 // NOMTE: instruction requires: mte
 // NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+
+stzgm x0, [x1]
+stzgm x1, [sp]
+stzgm xzr, [x2]
+
+// CHECK: stzgm x0, [x1]  // encoding: [0x20,0x00,0x20,0xd9]
+// CHECK: stzgm x1, [sp]  // encoding: [0xe1,0x03,0x20,0xd9]
+// CHECK: stzgm xzr, [x2] // encoding: [0x5f,0x00,0x20,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte

Modified: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt?rev=357397&r1=357396&r2=357397&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt Mon Apr  1 07:56:37 2019
@@ -407,6 +407,9 @@
 [0x20,0x00,0xa0,0xd9]
 [0xe1,0x03,0xa0,0xd9]
 [0x5f,0x00,0xa0,0xd9]
+[0x20,0x00,0x20,0xd9]
+[0xe1,0x03,0x20,0xd9]
+[0x5f,0x00,0x20,0xd9]
 
 # CHECK: ldgm x0, [x1]
 # CHECK: ldgm x1, [sp]
@@ -414,6 +417,9 @@
 # CHECK: stgm x0, [x1]
 # CHECK: stgm x1, [sp]
 # CHECK: stgm xzr, [x2]
+# CHECK: stzgm x0, [x1]
+# CHECK: stzgm x1, [sp]
+# CHECK: stzgm xzr, [x2]
 
 # NOMTE:      warning: invalid instruction encoding
 # NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]
@@ -427,6 +433,12 @@
 # NOMTE-NEXT: [0xe1,0x03,0xa0,0xd9]
 # NOMTE:      warning: invalid instruction encoding
 # NOMTE-NEXT: [0x5f,0x00,0xa0,0xd9]
+# NOMTE:      warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x00,0x20,0xd9]
+# NOMTE:      warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe1,0x03,0x20,0xd9]
+# NOMTE:      warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x00,0x20,0xd9]
 
 [0x60,0x76,0x08,0xd5]
 [0x81,0x76,0x08,0xd5]