[llvm] r357378 - [RISCV] Add seto pattern expansion
Luis Marques via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 1 02:54:14 PDT 2019
Author: luismarques
Date: Mon Apr 1 02:54:14 2019
New Revision: 357378
URL: http://llvm.org/viewvc/llvm-project?rev=357378&view=rev
Log:
[RISCV] Add seto pattern expansion
Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and
`fcmp ord` would be inefficient due to an unoptimized double negation.
Differential Revision: https://reviews.llvm.org/D59699
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll
llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Mon Apr 1 02:54:14 2019
@@ -137,9 +137,9 @@ RISCVTargetLowering::RISCVTargetLowering
setOperationAction(ISD::CTPOP, XLenVT, Expand);
ISD::CondCode FPCCToExtend[] = {
- ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETO, ISD::SETUEQ,
- ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE,
- ISD::SETGT, ISD::SETGE, ISD::SETNE};
+ ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
+ ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
+ ISD::SETGE, ISD::SETNE};
ISD::NodeType FPOpToExtend[] = {
ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM};
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td Mon Apr 1 02:54:14 2019
@@ -270,6 +270,10 @@ def : PatFpr64Fpr64<setole, FLE_D>;
// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
// Legalizer.
+def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
+ (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
+ (FEQ_D FPR64:$rs2, FPR64:$rs2))>;
+
def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
(SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
(FEQ_D FPR64:$rs2, FPR64:$rs2)),
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td Mon Apr 1 02:54:14 2019
@@ -324,6 +324,10 @@ def : PatFpr32Fpr32<setole, FLE_S>;
// handled by a RISC-V instruction and aren't expanded in the SelectionDAG
// Legalizer.
+def : Pat<(seto FPR32:$rs1, FPR32:$rs2),
+ (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
+ (FEQ_S FPR32:$rs2, FPR32:$rs2))>;
+
def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
(SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
(FEQ_S FPR32:$rs2, FPR32:$rs2)),
Modified: llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/double-br-fcmp.ll Mon Apr 1 02:54:14 2019
@@ -322,8 +322,6 @@ define void @br_fcmp_one(double %a, doub
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB7_2
; RV32IFD-NEXT: # %bb.1: # %if.else
@@ -344,8 +342,6 @@ define void @br_fcmp_one(double %a, doub
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1: # %if.else
@@ -377,8 +373,6 @@ define void @br_fcmp_ord(double %a, doub
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp)
@@ -396,8 +390,6 @@ define void @br_fcmp_ord(double %a, doub
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp)
Modified: llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/double-fcmp.ll Mon Apr 1 02:54:14 2019
@@ -159,8 +159,6 @@ define i32 @fcmp_one(double %a, double %
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
@@ -174,8 +172,6 @@ define i32 @fcmp_one(double %a, double %
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret
%1 = fcmp one double %a, %b
@@ -196,8 +192,6 @@ define i32 @fcmp_ord(double %a, double %
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -208,8 +202,6 @@ define i32 @fcmp_ord(double %a, double %
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: ret
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
Modified: llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/double-select-fcmp.ll Mon Apr 1 02:54:14 2019
@@ -221,8 +221,6 @@ define double @select_fcmp_one(double %a
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB6_2
; RV32IFD-NEXT: # %bb.1:
@@ -243,8 +241,6 @@ define double @select_fcmp_one(double %a
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB6_2
; RV64IFD-NEXT: # %bb.1:
@@ -270,8 +266,6 @@ define double @select_fcmp_ord(double %a
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
-; RV32IFD-NEXT: seqz a0, a0
-; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: bnez a0, .LBB7_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft0, ft1
@@ -289,8 +283,6 @@ define double @select_fcmp_ord(double %a
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
-; RV64IFD-NEXT: seqz a0, a0
-; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: bnez a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1
Modified: llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-br-fcmp.ll Mon Apr 1 02:54:14 2019
@@ -295,8 +295,6 @@ define void @br_fcmp_one(float %a, float
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1: # %if.else
@@ -317,8 +315,6 @@ define void @br_fcmp_one(float %a, float
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1: # %if.else
@@ -346,8 +342,6 @@ define void @br_fcmp_ord(float %a, float
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp)
@@ -365,8 +359,6 @@ define void @br_fcmp_ord(float %a, float
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp)
Modified: llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-fcmp.ll Mon Apr 1 02:54:14 2019
@@ -124,8 +124,6 @@ define i32 @fcmp_one(float %a, float %b)
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret
;
@@ -138,8 +136,6 @@ define i32 @fcmp_one(float %a, float %b)
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret
%1 = fcmp one float %a, %b
@@ -155,8 +151,6 @@ define i32 @fcmp_ord(float %a, float %b)
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ord:
@@ -166,8 +160,6 @@ define i32 @fcmp_ord(float %a, float %b)
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
Modified: llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll?rev=357378&r1=357377&r2=357378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-select-fcmp.ll Mon Apr 1 02:54:14 2019
@@ -175,8 +175,6 @@ define float @select_fcmp_one(float %a,
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB6_2
; RV32IF-NEXT: # %bb.1:
@@ -194,8 +192,6 @@ define float @select_fcmp_one(float %a,
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB6_2
; RV64IF-NEXT: # %bb.1:
@@ -216,8 +212,6 @@ define float @select_fcmp_ord(float %a,
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
-; RV32IF-NEXT: seqz a0, a0
-; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1
@@ -232,8 +226,6 @@ define float @select_fcmp_ord(float %a,
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
-; RV64IF-NEXT: seqz a0, a0
-; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1
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