[PATCH] D60041: [X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.

Sun Mar 31 23:16:13 PDT 2019

craig.topper marked an inline comment as done.
craig.topper added inline comments.

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Comment at: lib/Target/X86/X86SchedPredicates.td:68
+  CheckAll<[
+    CheckNumOperands<4>,
+    CheckAny<[
----------------
I was trying to use CheckNumOperands to distinquish Memory from Register. But I don't think it works correctly with the implicit operands that MachineInstrs have. The MCInst version and the MachineInstr version of CMOV have different number operands since MachineInstr models the EFLAGS implicit use but MCInst doesn't.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60041/new/

https://reviews.llvm.org/D60041