[PATCH] D60048: [InstCombine] eliminate commuted select-shuffles + binop (PR41304)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: lebedev.ri, RKSimon, ABataev.
Herald added subscribers: jdoerfert, hiraditya, mcrosier.
Herald added a project: LLVM.

If we have a commutable vector binop with inverted select-shuffles, we don't care about the order of the operands in each vector lane:

  LHS = shuffle V1, V2, <0, 5, 6, 3>
  RHS = shuffle V2, V1, <0, 5, 6, 3>
  LHS + RHS --> (V10+V20, V21+V11, V22+V12, V13+V23) --> V1 + V2

PR41304:
https://bugs.llvm.org/show_bug.cgi?id=41304
...is titled as an SLP enhancement, but at least for the given example, we can reduce that in instcombine because we are just eliminating shuffles.
As noted in the TODO, this could be generalized, but I haven't thought through those patterns completely, so this is limited to what appears to be always safe.


https://reviews.llvm.org/D60048

Files:
  llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
  llvm/test/Transforms/InstCombine/vec-binop-select.ll

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