[PATCH] D59952: [VPLAN] Remove option for stress testing.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli added a comment.

In D59952#1446685 <https://reviews.llvm.org/D59952#1446685>, @fhahn wrote:

> In D59952#1446670 <https://reviews.llvm.org/D59952#1446670>, @dcaballe wrote:
>
> > Yep, I agree on that we should keep the stress testing mechanism. It will be very useful to make sure that the construction and predication (and maybe other transformation) are robust enough since we can run it on loop nests that are not necessarily vectorizable.
> >  Something important, though, is that we shouldn't use this mechanism to bypass legality or pragma simd requirements to vectorize a loop, i.e., we shouldn't use it to generate actual vector code.
> >  What are you trying to achieve, Francesco?
>
>
> I suggested removing setting VF = 4 for VPlanStressTest now that we programmatically determine the VF, to streamline things a bit. In a way, just have VPlanStressTest mean: build a VPlan for any loop you can, with the automatically chosen VF.


yeah, this patch was a follow up on the comment from @fhahn : https://reviews.llvm.org/D57598#1444238

I might have misunderstood his request. I will abandon the patch.

Thank you,

Francesco


Repository:
  rL LLVM

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https://reviews.llvm.org/D59952