[llvm] r357084 - AMDGPU: Don't hardcode num defs for MUBUF instructions

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Mar 27 09:12:29 2019
New Revision: 357084

URL: http://llvm.org/viewvc/llvm-project?rev=357084&view=rev
Log:
AMDGPU: Don't hardcode num defs for MUBUF instructions

This shouldn't change anything since the no-ret atomics are selected
later.

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=357084&r1=357083&r2=357084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Mar 27 09:12:29 2019
@@ -226,8 +226,8 @@ bool SIInstrInfo::areLoadsFromSameBasePt
     // getNamedOperandIdx returns the index for MachineInstrs.  Since they
     // include the output in the operand list, but SDNodes don't, we need to
     // subtract the index by one.
-    --OffIdx0;
-    --OffIdx1;
+    OffIdx0 -= get(Opc0).NumDefs;
+    OffIdx1 -= get(Opc1).NumDefs;
 
     SDValue Off0 = Load0->getOperand(OffIdx0);
     SDValue Off1 = Load1->getOperand(OffIdx1);