[llvm] r357073 - AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed Mar 27 08:41:00 2019
New Revision: 357073

URL: http://llvm.org/viewvc/llvm-project?rev=357073&view=rev
Log:
AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics

The offset operand index is different for atomics.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=357073&r1=357072&r2=357073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Mar 27 08:41:00 2019
@@ -167,12 +167,19 @@ bool SIInstrInfo::areLoadsFromSameBasePt
     // Skip read2 / write2 variants for simplicity.
     // TODO: We should report true if the used offsets are adjacent (excluded
     // st64 versions).
-    if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
-        AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
+    int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
+    int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
+    if (Offset0Idx == -1 || Offset1Idx == -1)
       return false;
 
-    Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
-    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
+    // XXX - be careful of datalesss loads
+    // getNamedOperandIdx returns the index for MachineInstrs.  Since they
+    // include the output in the operand list, but SDNodes don't, we need to
+    // subtract the index by one.
+    Offset0Idx -= get(Opc0).NumDefs;
+    Offset1Idx -= get(Opc1).NumDefs;
+    Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
+    Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
     return true;
   }
 

Added: llvm/trunk/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll?rev=357073&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/are-loads-from-same-base-ptr.ll Wed Mar 27 08:41:00 2019
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; TII::areLoadsFromSameBasePtr failed because the offset for atomics
+; is different from a normal load due to the data operand.
+
+; GCN-LABEL: {{^}}are_loads_from_same_base_ptr_ds_atomic:
+; GCN: global_load_dword
+; GCN: ds_min_u32
+; GCN: ds_max_u32
+define amdgpu_kernel void @are_loads_from_same_base_ptr_ds_atomic(i32 addrspace(1)* %arg0, i32 addrspace(3)* noalias %ptr0) #0 {
+  %tmp1 = load volatile i32, i32 addrspace(1)* %arg0
+  %tmp2 = atomicrmw umin i32 addrspace(3)* %ptr0, i32 %tmp1 seq_cst
+  %tmp3 = atomicrmw umax i32 addrspace(3)* %ptr0, i32 %tmp1 seq_cst
+  ret void
+}
+
+attributes #0 = { nounwind }