[PATCH] D59851: AMDGPU: Fix areLoadsFromSameBasePtr for DS atomics

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked 2 inline comments as done.
arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:178-179
+    // subtract the index by one.
+    --Offset0Idx;
+    --Offset1Idx;
+    Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
----------------
These should use the NumDefs from the instr desc in case the no-ret atomics are used, although those are inserted later currently


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:181
+    Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
+    Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset0Idx))->getZExtValue();
     return true;
----------------
The index used needs to be fixed for inst 1


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59851/new/

https://reviews.llvm.org/D59851