[PATCH] D59842: RegScavenger: Fix !AllowSpill if no regs are available

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: qcolombet, MatzeB, thegameg.
Herald added subscribers: nhaehnle, wdng, jvesely.
arsenm added parent revisions: D59840:  AMDGPU: Enable the scavenger for large frames, D59836: PEI: Delay checking requiresFrameIndexReplacementScavenging.

Fixes option added in r354816.


https://reviews.llvm.org/D59842

Files:
  lib/CodeGen/RegisterScavenging.cpp
  test/CodeGen/AMDGPU/spill-offset-calculation.ll


Index: test/CodeGen/AMDGPU/spill-offset-calculation.ll
===================================================================
--- test/CodeGen/AMDGPU/spill-offset-calculation.ll
+++ test/CodeGen/AMDGPU/spill-offset-calculation.ll
@@ -48,6 +48,48 @@
   ret void
 }
 
+; CHECK-LABEL: test_sgpr_offset_kernel_scavenge_fail
+define amdgpu_kernel void @test_sgpr_offset_kernel_scavenge_fail() {
+entry:
+  ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
+  ; fit in the instruction, and has to live in the SGPR offset.
+  %alloca = alloca i8, i32 4092, align 4, addrspace(5)
+  %buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
+
+  %aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
+
+  ; 0x40000 / 64 = 4096 (for wave64)
+  ; CHECK: s_add_u32 s6, s7, 0x40000
+  ; CHECK: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s6 ; 4-byte Folded Spill
+  %a = load volatile i32, i32 addrspace(5)* %aptr
+
+  ; Force %a to spill
+  call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"()
+
+  ; CHECK: s_add_u32 s7, s7, 0x40000
+  ; CHECK: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s7 ; 4-byte Folded Reload
+  ; CHECK: s_sub_u32 s7, s7, 0x40000
+
+  ; No SGPRs are available to scavenge during reload
+  call void asm sideeffect "",
+    "~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
+    ,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
+    ,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
+    ,~{s30},~{s31},~{s32},~{s33},~{s34},~{s35},~{s36},~{s37},~{s38},~{s39}
+    ,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
+    ,~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58},~{s59}
+    ,~{s60},~{s61},~{s62},~{s63},~{s64},~{s65},~{s66},~{s67},~{s68},~{s69}
+    ,~{s70},~{s71},~{s72},~{s73},~{s74},~{s75},~{s76},~{s77},~{s78},~{s79}
+    ,~{s80},~{s81},~{s82},~{s83},~{s84},~{s85},~{s86},~{s87},~{s88},~{s89}
+    ,~{s90},~{s91},~{s92},~{s93},~{s94},~{s95},~{s96},~{s97},~{s98},~{s99}
+    ,~{s100},~{s101},~{vcc}"() #1
+
+  %outptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
+  store volatile i32 %a, i32 addrspace(5)* %outptr
+
+  ret void
+}
+
 ; CHECK-LABEL: test_sgpr_offset_subregs_kernel
 define amdgpu_kernel void @test_sgpr_offset_subregs_kernel() {
 entry:
Index: lib/CodeGen/RegisterScavenging.cpp
===================================================================
--- lib/CodeGen/RegisterScavenging.cpp
+++ lib/CodeGen/RegisterScavenging.cpp
@@ -308,7 +308,8 @@
                                        unsigned InstrLimit,
                                        MachineBasicBlock::iterator &UseMI) {
   int Survivor = Candidates.find_first();
-  assert(Survivor > 0 && "No candidates for scavenging");
+  if (Survivor <= 0)
+    return 0; // No candidates for scavenging
 
   MachineBasicBlock::iterator ME = MBB->getFirstTerminator();
   assert(StartMI != ME && "MI already at terminator");
@@ -557,6 +558,10 @@
   // Find the register whose use is furthest away.
   MachineBasicBlock::iterator UseMI;
   unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
+  if (SReg == 0) {
+    assert(!AllowSpill && "No candidates for scavenging");
+    return 0;
+  }
 
   // If we found an unused register there is no reason to spill it.
   if (!isRegUsed(SReg)) {


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