[PATCH] D59758: [DAGCombiner] Combine OR as ADD when no common bits are set

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D59758#1443074 <https://reviews.llvm.org/D59758#1443074>, @bjope wrote:

> In D59758#1442959 <https://reviews.llvm.org/D59758#1442959>, @spatel wrote:
>
> > In D59758#1441124 <https://reviews.llvm.org/D59758#1441124>, @bjope wrote:
> >
> > > Hello reviewers! Do you think this is a good idea?
> >
> >
> > It's an interesting idea. :)
> >
> > > I've mostly seen improvements for our OOT target when doing this, but for example llvm/test/CodeGen/X86/split-store.ll also exposes a case when we trigger a rewrite into using SUB.
> >
> > Yes, we'd classify that as a slight regression for x86.
>
>
> Isn't split-store.ll showing an improvement (we get one subb instead of andb+orb)?


Yes - sorry, I reversed that with signbit-shift.ll. So we would call signbit-shift.ll a slight regression because of the extra mov instruction. We are probably missing a generic combine. Might be similar to the hexagon diff?

> However, signbit-shift.ll might show a regression (since we get one more instruction and use an extra register). However, I'm not that familiar with the vector instructions to understand if it really is a regression (maybe those movdqa instructions are easier to schedule, or having shorter latency or something).




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