[PATCH] D59799: [wip][mips] Use AltOrders to prevent using odd FP-registers

[Simon Atanasyan via Phabricator via llvm-commits]

atanasyan created this revision.
atanasyan added reviewers: Petar.Avramovic, petarj, sdardis, dsanders.
Herald added subscribers: dexonsmith, jrtc27, hiraditya, arichardson, inglorion, mehdi_amini.
Herald added a project: LLVM.

To disable using of odd floating-point registers (O32 ABI and -mno-odd-spreg command line option) such registers and their super-registers added to the set of reserved registers. In general, it works. But there is at least one problem - in case of enabled machine verifier pass some floating-point tests failed because live ranges of register units that are reserved is not empty and verification pass failed with "Live segment doesn't end at a valid instruction" error message.

There is D35985 <https://reviews.llvm.org/D35985> patch which tries to solve the problem by explicit removing of register units. This solution did not get approval.

I would like to use another approach for prevent using odd floating-point registers - define `AltOrders` and `AltOrderSelect` for MIPS floating point register classes. Such `AltOrders` contains reduced set of registers. At first glance, such solution does not break any test cases and allows enabling machine instruction verification for all MIPS test cases.

Does anybody see any problems on this way?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D59799

Files:
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.td
  llvm/test/CodeGen/Mips/no-odd-spreg-msa.ll

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