[llvm] r356952 - AMDGPU: Set hasSideEffects 0 on _term instructions
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 14:10:12 PDT 2019
Author: arsenm
Date: Mon Mar 25 14:10:12 2019
New Revision: 356952
URL: http://llvm.org/viewvc/llvm-project?rev=356952&view=rev
Log:
AMDGPU: Set hasSideEffects 0 on _term instructions
These were defaulting to true, but they are just wrappers around bit
operations. This avoids regressions in the exec mask optimization
passes in a future commit.
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=356952&r1=356951&r2=356952&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Mon Mar 25 14:10:12 2019
@@ -172,12 +172,14 @@ def S_MOV_B64_term : SPseudoInstSI<(outs
(ins SSrc_b64:$src0)> {
let isAsCheapAsAMove = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
}
def S_XOR_B64_term : SPseudoInstSI<(outs SReg_64:$dst),
(ins SSrc_b64:$src0, SSrc_b64:$src1)> {
let isAsCheapAsAMove = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
let Defs = [SCC];
}
@@ -185,6 +187,7 @@ def S_ANDN2_B64_term : SPseudoInstSI<(ou
(ins SSrc_b64:$src0, SSrc_b64:$src1)> {
let isAsCheapAsAMove = 1;
let isTerminator = 1;
+ let hasSideEffects = 0;
}
def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),
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