[llvm] r356883 - [MIPS GlobalISel] Add floating point register bank
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 25 04:30:46 PDT 2019
Author: petar.avramovic
Date: Mon Mar 25 04:30:46 2019
New Revision: 356883
URL: http://llvm.org/viewvc/llvm-project?rev=356883&view=rev
Log:
[MIPS GlobalISel] Add floating point register bank
Add floating point register bank for MIPS32.
Implement getRegBankFromRegClass for float register classes.
Differential Revision: https://reviews.llvm.org/D59643
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterBanks.td
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp?rev=356883&r1=356882&r2=356883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp Mon Mar 25 04:30:46 2019
@@ -62,6 +62,11 @@ const RegisterBank &MipsRegisterBankInfo
case Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID:
case Mips::SP32RegClassID:
return getRegBank(Mips::GPRBRegBankID);
+ case Mips::FGRCCRegClassID:
+ case Mips::FGR64RegClassID:
+ case Mips::AFGR64RegClassID:
+ case Mips::AFGR64_and_OddSPRegClassID:
+ return getRegBank(Mips::FPRBRegBankID);
default:
llvm_unreachable("Register class not supported");
}
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBanks.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBanks.td?rev=356883&r1=356882&r2=356883&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBanks.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBanks.td Mon Mar 25 04:30:46 2019
@@ -10,3 +10,5 @@
//===----------------------------------------------------------------------===//
def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
+
+def FPRBRegBank : RegisterBank<"FPRB", [FGR64, AFGR64]>;
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir?rev=356883&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/float_args.mir Mon Mar 25 04:30:46 2019
@@ -0,0 +1,296 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+
+--- |
+
+ define void @float_in_fpr() {entry: ret void}
+ define void @double_in_fpr() {entry: ret void}
+ define void @float_in_gpr() {entry: ret void}
+ define void @double_in_gpr() {entry: ret void}
+ define void @call_float_in_fpr() {entry: ret void}
+ define void @call_double_in_fpr() {entry: ret void}
+ define void @call_float_in_gpr() {entry: ret void}
+ define void @call_double_in_gpr() {entry: ret void}
+
+...
+---
+name: float_in_fpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: float_in_fpr
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP32: $f0 = COPY [[COPY]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_in_fpr
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP64: $f0 = COPY [[COPY]](s32)
+ ; FP64: RetRA implicit $f0
+ %1:_(s32) = COPY $f14
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
+---
+name: double_in_fpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: double_in_fpr
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP32: $d0 = COPY [[COPY]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_in_fpr
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP64: $d0 = COPY [[COPY]](s64)
+ ; FP64: RetRA implicit $d0
+ %1:_(s64) = COPY $d7
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
+---
+name: float_in_gpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; FP32-LABEL: name: float_in_gpr
+ ; FP32: liveins: $a0, $a1
+ ; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
+ ; FP32: $f0 = COPY [[MTC1_]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: float_in_gpr
+ ; FP64: liveins: $a0, $a1
+ ; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
+ ; FP64: $f0 = COPY [[MTC1_]](s32)
+ ; FP64: RetRA implicit $f0
+ %1:fgr32(s32) = MTC1 $a1
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
+---
+name: double_in_gpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a2, $a3
+
+ ; FP32-LABEL: name: double_in_gpr
+ ; FP32: liveins: $a0, $a2, $a3
+ ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
+ ; FP32: $d0 = COPY [[BuildPairF64_]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: double_in_gpr
+ ; FP64: liveins: $a0, $a2, $a3
+ ; FP64: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
+ ; FP64: $d0 = COPY [[BuildPairF64_]](s64)
+ ; FP64: RetRA implicit $d0
+ %1:afgr64(s64) = BuildPairF64 $a2, $a3
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
+---
+name: call_float_in_fpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12, $f14
+
+ ; FP32-LABEL: name: call_float_in_fpr
+ ; FP32: liveins: $f12, $f14
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $f12 = COPY [[COPY]](s32)
+ ; FP32: $f14 = COPY [[COPY1]](s32)
+ ; FP32: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP32: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f0
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $f0 = COPY [[COPY2]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: call_float_in_fpr
+ ; FP64: liveins: $f12, $f14
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $f12 = COPY [[COPY]](s32)
+ ; FP64: $f14 = COPY [[COPY1]](s32)
+ ; FP64: JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ ; FP64: [[COPY2:%[0-9]+]]:fprb(s32) = COPY $f0
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $f0 = COPY [[COPY2]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = COPY $f14
+ ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ $f12 = COPY %0(s32)
+ $f14 = COPY %1(s32)
+ JAL @float_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit $f14, implicit-def $f0
+ %2:_(s32) = COPY $f0
+ ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: call_double_in_fpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6, $d7
+
+ ; FP32-LABEL: name: call_double_in_fpr
+ ; FP32: liveins: $d6, $d7
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $d6 = COPY [[COPY]](s64)
+ ; FP32: $d7 = COPY [[COPY1]](s64)
+ ; FP32: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP32: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $d0
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $d0 = COPY [[COPY2]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: call_double_in_fpr
+ ; FP64: liveins: $d6, $d7
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d7
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $d6 = COPY [[COPY]](s64)
+ ; FP64: $d7 = COPY [[COPY1]](s64)
+ ; FP64: JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ ; FP64: [[COPY2:%[0-9]+]]:fprb(s64) = COPY $d0
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $d0 = COPY [[COPY2]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = COPY $d7
+ ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ $d6 = COPY %0(s64)
+ $d7 = COPY %1(s64)
+ JAL @double_in_fpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $d6, implicit $d7, implicit-def $d0
+ %2:_(s64) = COPY $d0
+ ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+---
+name: call_float_in_gpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a1
+
+ ; FP32-LABEL: name: call_float_in_gpr
+ ; FP32: liveins: $a0, $a1
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP32: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $a0 = COPY [[COPY]](s32)
+ ; FP32: $a1 = MFC1 [[MTC1_]](s32)
+ ; FP32: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f0
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $f0 = COPY [[COPY1]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: call_float_in_gpr
+ ; FP64: liveins: $a0, $a1
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP64: [[MTC1_:%[0-9]+]]:fgr32(s32) = MTC1 $a1
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $a0 = COPY [[COPY]](s32)
+ ; FP64: $a1 = MFC1 [[MTC1_]](s32)
+ ; FP64: JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f0
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $f0 = COPY [[COPY1]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $a0
+ %1:fgr32(s32) = MTC1 $a1
+ ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ $a0 = COPY %0(s32)
+ $a1 = MFC1 %1(s32)
+ JAL @float_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $f0
+ %2:_(s32) = COPY $f0
+ ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ $f0 = COPY %2(s32)
+ RetRA implicit $f0
+
+...
+---
+name: call_double_in_gpr
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $a0, $a2, $a3
+
+ ; FP32-LABEL: name: call_double_in_gpr
+ ; FP32: liveins: $a0, $a2, $a3
+ ; FP32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
+ ; FP32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $a0 = COPY [[COPY]](s32)
+ ; FP32: $a3 = ExtractElementF64 [[BuildPairF64_]](s64), 1
+ ; FP32: $a2 = ExtractElementF64 [[BuildPairF64_]](s64), 0
+ ; FP32: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ ; FP32: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d0
+ ; FP32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP32: $d0 = COPY [[COPY1]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: call_double_in_gpr
+ ; FP64: liveins: $a0, $a2, $a3
+ ; FP64: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; FP64: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 $a2, $a3
+ ; FP64: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $a0 = COPY [[COPY]](s32)
+ ; FP64: $a3 = ExtractElementF64 [[BuildPairF64_]](s64), 1
+ ; FP64: $a2 = ExtractElementF64 [[BuildPairF64_]](s64), 0
+ ; FP64: JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ ; FP64: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $d0
+ ; FP64: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; FP64: $d0 = COPY [[COPY1]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s32) = COPY $a0
+ %1:afgr64(s64) = BuildPairF64 $a2, $a3
+ ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
+ $a0 = COPY %0(s32)
+ $a3 = ExtractElementF64 %1(s64), 1
+ $a2 = ExtractElementF64 %1(s64), 0
+ JAL @double_in_gpr, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $d0
+ %2:_(s64) = COPY $d0
+ ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ $d0 = COPY %2(s64)
+ RetRA implicit $d0
+
+...
+
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