[PATCH] D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 192061.
c-rhodes added a comment.

Removed unnecessary parenthesis.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59636/new/

https://reviews.llvm.org/D59636

Files:
  lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  test/MC/AArch64/SVE/ldr-diagnostics.s
  test/MC/AArch64/SVE/movprfx-diagnostics.s
  test/MC/AArch64/SVE/str-diagnostics.s


Index: test/MC/AArch64/SVE/str-diagnostics.s
===================================================================
--- test/MC/AArch64/SVE/str-diagnostics.s
+++ test/MC/AArch64/SVE/str-diagnostics.s
@@ -22,3 +22,11 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
 // CHECK-NEXT: str z0, [x0, #256, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Unexpected element width suffix
+
+str z0.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
+// CHECK-NEXT: str z0.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: test/MC/AArch64/SVE/movprfx-diagnostics.s
===================================================================
--- test/MC/AArch64/SVE/movprfx-diagnostics.s
+++ test/MC/AArch64/SVE/movprfx-diagnostics.s
@@ -1,6 +1,25 @@
 // RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve  2>&1 < %s | FileCheck %s
 
 // ------------------------------------------------------------------------- //
+// Type suffix on unpredicated movprfx
+
+movprfx z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.b, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
+// CHECK-NEXT: movprfx z0, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Different destination register (unary)
 
 movprfx z0, z1
Index: test/MC/AArch64/SVE/ldr-diagnostics.s
===================================================================
--- test/MC/AArch64/SVE/ldr-diagnostics.s
+++ test/MC/AArch64/SVE/ldr-diagnostics.s
@@ -22,3 +22,11 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-256, 255].
 // CHECK-NEXT: ldr z0, [x0, #256, MUL VL]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Unexpected element width suffix
+
+ldr z0.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected register without element width suffix
+// CHECK-NEXT: ldr z0.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1090,8 +1090,7 @@
     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
       return DiagnosticPredicateTy::NoMatch;
 
-    if (isSVEVectorReg<Class>() &&
-           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+    if (isSVEVectorReg<Class>() && Reg.ElementWidth == ElementWidth)
       return DiagnosticPredicateTy::Match;
 
     return DiagnosticPredicateTy::NearMatch;
@@ -4442,7 +4441,7 @@
   case Match_InvalidZPR64LSL64:
     return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'");
   case Match_InvalidZPR0:
-    return Error(Loc, "expected register without element width sufix");
+    return Error(Loc, "expected register without element width suffix");
   case Match_InvalidZPR8:
   case Match_InvalidZPR16:
   case Match_InvalidZPR32:


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