[llvm] r356868 - [X86] Remove GetLo8XForm and use GetLo32XForm instead. NFCI

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 24 23:53:44 PDT 2019


Author: ctopper
Date: Sun Mar 24 23:53:44 2019
New Revision: 356868

URL: http://llvm.org/viewvc/llvm-project?rev=356868&view=rev
Log:
[X86] Remove GetLo8XForm and use GetLo32XForm instead. NFCI

We were using this to create an AND32ri8 node from a 64-bit and, but that node
normally still uses a 32-bit immediate. So we should just truncate the existing
immediate to i32. We already verified it has the same value in bits 31:7.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=356868&r1=356867&r2=356868&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Sun Mar 24 23:53:44 2019
@@ -19,11 +19,6 @@ def GetLo32XForm : SDNodeXForm<imm, [{
   return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N));
 }]>;
 
-def GetLo8XForm : SDNodeXForm<imm, [{
-  // Transformation function: get the low 8 bits.
-  return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
-}]>;
-
 
 //===----------------------------------------------------------------------===//
 // Random Pseudo Instructions.
@@ -1523,7 +1518,7 @@ def : Pat<(and GR64:$src, i64immZExt32SE
             (i64 0),
             (AND32ri8
               (EXTRACT_SUBREG GR64:$src, sub_32bit),
-              (i32 (GetLo8XForm imm:$imm))),
+              (i32 (GetLo32XForm imm:$imm))),
             sub_32bit)>;
 
 def : Pat<(and GR64:$src, i64immZExt32:$imm),




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