[PATCH] D59680: [ARM] Don't form "ands" when it isn't scheduled correctly.

[Eli Friedman via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL356809: [ARM] Don't form "ands" when it isn't scheduled correctly. (authored by efriedma, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D59680?vs=191808&id=191944#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59680/new/

https://reviews.llvm.org/D59680

Files:
  llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/trunk/test/CodeGen/ARM/tst-peephole.mir


Index: llvm/trunk/test/CodeGen/ARM/tst-peephole.mir
===================================================================
--- llvm/trunk/test/CodeGen/ARM/tst-peephole.mir
+++ llvm/trunk/test/CodeGen/ARM/tst-peephole.mir
@@ -0,0 +1,54 @@
+# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s
+
+# The and -> ands transform is sensitive to scheduling; make sure we don't
+# transform cases which aren't legal.
+
+# CHECK-LABEL: name: foo_transform
+# CHECK:      %2:gpr = ANDri %0, 1, 14, $noreg, def $cpsr
+# CHECK-NEXT: %3:gpr = MOVCCi16 %1, 5, 0, $cpsr
+
+# CHECK-LABEL: name: foo_notransform
+# CHECK:      TSTri %0, 1, 14, $noreg, implicit-def $cpsr
+# CHECK-NEXT: %2:gpr = MOVCCi16 %1, 5, 0, $cpsr
+
+--- |
+  target triple = "armv7-unknown-unknown"
+  define i32 @foo_transform(i32 %in) {
+    ret i32 undef
+  }
+  define i32 @foo_notransform(i32 %in) {
+    ret i32 undef
+  }
+
+...
+---
+name:            foo_transform
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $r0
+
+    %1:gpr = COPY $r0
+    %2:gpr = MOVi 4, 14, $noreg, $noreg
+    %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
+    TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
+    %3:gpr = MOVCCi16 %2, 5, 0, $cpsr
+    $r0 = COPY killed %3
+    $r1 = COPY killed %4
+    BX_RET 14, $noreg, implicit $r0, implicit $r1
+...
+name:            foo_notransform
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $r0
+
+    %1:gpr = COPY $r0
+    %2:gpr = MOVi 4, 14, $noreg, $noreg
+    TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr
+    %3:gpr = MOVCCi16 %2, 5, 0, $cpsr
+    %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg
+    $r0 = COPY killed %3
+    $r1 = COPY killed %4
+    BX_RET 14, $noreg, implicit $r0, implicit $r1
+
Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2869,7 +2869,15 @@
       // change. We can't do this transformation.
       return false;
 
-  } while (I != B);
+    if (I == B) {
+      // In some cases, we scan the use-list of an instruction for an AND;
+      // that AND is in the same BB, but may not be scheduled before the
+      // corresponding TST.  In that case, bail out.
+      //
+      // FIXME: We could try to reschedule the AND.
+      return false;
+    }
+  } while (true);
 
   // Return false if no candidates exist.
   if (!MI && !SubAdd)


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