[PATCH] D59662: [X86] Use xmm registers to implement 64-bit popcnt on 32-bit targets if possible if popcnt instruction is not available

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked an inline comment as done.
craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:26715
+          DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, N->getOperand(0));
+      Wide = DAG.getNode(N->getOpcode(), dl, MVT::v2i64, Wide);
+      // Bit count should fit in 32-bits, extract it as that and then zero
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spatel wrote:
> Clearer to make this use the constant opcode getNode(ISD::CTPOP...) instead of using N->getOpcode() again.
Yeah I'll change that. When I wrote it I was thinking we might want to do this for cttz and ctlz too, but those expanded still use bsr/bsf or lzcnt/tzcnt so the vector version is probably worse.


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  https://reviews.llvm.org/D59662/new/

https://reviews.llvm.org/D59662