[PATCH] D59680: [ARM] Don't form "ands" when it isn't scheduled correctly.

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for putting the fix together.

If I understand correctly, if cpsr was not used between the TST and the AND, this would be OK to remove. Do you know if the isSafe loop could/should catch this? This whole function mostly expects the CmpMI to be after MI, so I think this fix is a good one in any case.


Repository:
  rL LLVM

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https://reviews.llvm.org/D59680