[PATCH] D52010: RegAllocFast: Rewrite and improve

Thu Mar 21 13:51:02 PDT 2019

arsenm added inline comments.

================
Comment at: lib/CodeGen/RegAllocFast.cpp:390-393
   // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
   // of spilling here is deterministic, if arbitrary.
-  for (LiveReg &LR : LiveVirtRegs) {
-    if (!LR.PhysReg)
+  MachineBasicBlock::iterator InsertBefore = getMBBBeginInsertionPoint(MBB);
+  for (const LiveReg &LR : LiveVirtRegs) {
----------------
This is problematic for AMDGPU. The order of the spills matters in the case the registers used are needed to restore the exec mask in the target block. Additionally, getMBBBeginInsertionPoint should be using SkipPHIsAndLabels so that isBasicBlockPrologue is respected.

Because of this the updates to test/CodeGen/AMDGPU/control-flow-fastregalloc.ll are wrong

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D52010/new/

https://reviews.llvm.org/D52010