[PATCH] D59655: [AArch64] Split the neon.addp intrinsic into integer and fp variants

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, eli.friedman, t.p.northover.
aemerson added projects: LLVM, clang.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar.

This is the result of discussions on the list about how to deal with intrinsics which require codegen to disambiguate them via only the integer/fp overloads. It causes problems for GlobalISel as some of that information is lost during translation, while with other operations like IR instructions the information is encoded into the instruction opcode.

This patch changes clang to emit the new faddp intrinsic if the vector operands to the builtin have FP element types. LLVM IR AutoUpgrade has been taught to upgrade existing calls to aarch64.neon.addp with fp vector arguments, and we remove the workarounds introduced for GlobalISel in r355865.

This is a more permanent solution to PR40968.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D59655

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-neon-intrinsics.c
  clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
  llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
  llvm/test/CodeGen/AArch64/GlobalISel/fallback-ambiguous-addp-intrinsic.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
  llvm/test/CodeGen/AArch64/arm64-vadd.ll
  llvm/test/CodeGen/AArch64/autoupgrade-aarch64-neon-addp-float.ll

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