[llvm] r356661 - [Thumb] Fix infinite loop in ABS expansion (PR41160)

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Mar 21 05:41:18 2019
New Revision: 356661

URL: http://llvm.org/viewvc/llvm-project?rev=356661&view=rev
Log:
[Thumb] Fix infinite loop in ABS expansion (PR41160)

Don't expand ISD::ABS node if its legal.

Added:
    llvm/trunk/test/CodeGen/Thumb/iabs-vector.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=356661&r1=356660&r2=356661&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Mar 21 05:41:18 2019
@@ -10391,9 +10391,12 @@ static SDValue PerformABSCombine(SDNode
   SelectionDAG &DAG = DCI.DAG;
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
-  if (!TLI.expandABS(N, res, DAG))
+  if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0)))
     return SDValue();
 
+  if (!TLI.expandABS(N, res, DAG))
+      return SDValue();
+
   return res;
 }
 

Added: llvm/trunk/test/CodeGen/Thumb/iabs-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/iabs-vector.ll?rev=356661&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/iabs-vector.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/iabs-vector.ll Thu Mar 21 05:41:18 2019
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv7--- | FileCheck %s
+
+define void @PR41160(<8 x i32>* %p) nounwind {
+; CHECK-LABEL: PR41160:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.8 {d16, d17}, [r0]
+; CHECK-NEXT:    vabs.s32 q8, q8
+; CHECK-NEXT:    vst1.8 {d16, d17}, [r0]!
+; CHECK-NEXT:    vld1.8 {d16, d17}, [r0]
+; CHECK-NEXT:    vabs.s32 q8, q8
+; CHECK-NEXT:    vst1.8 {d16, d17}, [r0]
+; CHECK-NEXT:    bx lr
+  %tmp1 = load <8 x i32>, <8 x i32>* %p, align 1
+  %tmp2 = icmp slt <8 x i32> %tmp1, zeroinitializer
+  %tmp3 = sub nsw <8 x i32> zeroinitializer, %tmp1
+  %tmp4 = select <8 x i1> %tmp2, <8 x i32> %tmp3, <8 x i32> %tmp1
+  store <8 x i32> %tmp4, <8 x i32>* %p, align 1
+  ret void
+}