[PATCH] D59636: [AArch64][SVE] Asm: error on unexpected SVE vector register type suffix

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added a reviewer: sdesmalen.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett, javed.absar.
Herald added a project: LLVM.

This patch fixes an assembler bug that allowed SVE vector registers to
contain a type suffix when not expected. It affects all SVE instructions
using vector registers where the type should not be specified.

The following are examples of what was previously valid:

  movprfx z0.b, z0.b
  movprfx z0.b, z0.s

These instructions are now erroneous.


https://reviews.llvm.org/D59636

Files:
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/test/MC/AArch64/SVE/movprfx-diagnostics.s


Index: llvm/test/MC/AArch64/SVE/movprfx-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SVE/movprfx-diagnostics.s
+++ llvm/test/MC/AArch64/SVE/movprfx-diagnostics.s
@@ -1,6 +1,20 @@
 // RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve  2>&1 < %s | FileCheck %s
 
 // ------------------------------------------------------------------------- //
+// Type suffix on unpredicated movprfx
+
+movprfx z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0.b, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: movprfx z0.b, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
 // Different destination register (unary)
 
 movprfx z0, z1
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1090,8 +1090,7 @@
     if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
       return DiagnosticPredicateTy::NoMatch;
 
-    if (isSVEVectorReg<Class>() &&
-           (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+    if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
       return DiagnosticPredicateTy::Match;
 
     return DiagnosticPredicateTy::NearMatch;


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