[PATCH] D59577: [SelectionDAG] Add scalarization of ABS node.

[Simon Pilgrim via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL356656: [SelectionDAG] Add scalarization of ABS node (PR41149) (authored by RKSimon, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D59577?vs=191648&id=191660#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59577/new/

https://reviews.llvm.org/D59577

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/trunk/test/CodeGen/WebAssembly/PR41149.ll


Index: llvm/trunk/test/CodeGen/WebAssembly/PR41149.ll
===================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/PR41149.ll
+++ llvm/trunk/test/CodeGen/WebAssembly/PR41149.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s -mtriple=wasm32-unknown-unknown | FileCheck %s
+
+; Regression test for PR41149.
+
+define void @mod() {
+; CHECK-LABEL: mod:
+; CHECK-NEXT: .functype mod () -> ()
+; CHECK:      local.get       0
+; CHECK-NEXT: local.get       0
+; CHECK-NEXT: i32.load8_s     0
+; CHECK-NEXT: local.tee       0
+; CHECK-NEXT: local.get       0
+; CHECK-NEXT: i32.const       31
+; CHECK-NEXT: i32.shr_s
+; CHECK-NEXT: local.tee       0
+; CHECK-NEXT: i32.add
+; CHECK-NEXT: local.get       0
+; CHECK-NEXT: i32.xor
+; CHECK-NEXT: i32.store8      0
+  %tmp = load <4 x i8>, <4 x i8>* undef
+  %tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
+  %tmp3 = sub <4 x i8> zeroinitializer, %tmp
+  %tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
+  store <4 x i8> %tmp4, <4 x i8>* undef
+  ret void
+}
+
Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -68,6 +68,7 @@
   case ISD::ZERO_EXTEND_VECTOR_INREG:
     R = ScalarizeVecRes_VecInregOp(N);
     break;
+  case ISD::ABS:
   case ISD::ANY_EXTEND:
   case ISD::BITREVERSE:
   case ISD::BSWAP:


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