[PATCH] D59626: Add MachineDCE pass after RenameIndependentSubregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: arsenm, sunfish.
Herald added subscribers: jdoerfert, javed.absar, nhaehnle, wdng, jvesely, qcolombet.

Detect dead lanes can create some dead defs. Then RenameIndependentSubregs
will break a REG_SEQUENCE which may use these dead defs. At this point
a dead instruction can be removed but we do not run a DCE anymore.

MachineDCE was only running before live variable analysis. The patch
adds a mean to preserve LiveIntervals and SlotIndexes in case it works
past this.


https://reviews.llvm.org/D59626

Files:
  lib/CodeGen/DeadMachineInstructionElim.cpp
  lib/CodeGen/TargetPassConfig.cpp
  test/CodeGen/AArch64/O3-pipeline.ll
  test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
  test/CodeGen/AMDGPU/dead-lane.mir
  test/CodeGen/AMDGPU/salu-to-valu.ll
  test/CodeGen/AMDGPU/sdwa-peephole.ll
  test/CodeGen/AMDGPU/shrink-carry.mir
  test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
  test/CodeGen/ARM/select-imm.ll
  test/CodeGen/Hexagon/v6-unaligned-spill.ll
  test/CodeGen/X86/O3-pipeline.ll
  test/CodeGen/X86/llc-start-stop-instance.ll
  test/CodeGen/X86/speculative-load-hardening-gather.ll
  test/CodeGen/X86/speculative-load-hardening-indirect.ll
  test/CodeGen/X86/speculative-load-hardening.ll
  test/CodeGen/X86/tail-dup-merge-loop-headers.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D59626.191622.patch
Type: text/x-patch
Size: 41189 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190321/40c8ecae/attachment.bin>