[PATCH] D59577: [SelectionDAG] Add scalarization of ABS node.
Ivan Kulagin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 23:13:14 PDT 2019
ikulagin updated this revision to Diff 191635.
ikulagin added a comment.
Herald added subscribers: aheejin, jgravelle-google, sbc100, dschuff.
Add test case for PR41149
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D59577/new/
https://reviews.llvm.org/D59577
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/test/CodeGen/WebAssembly/PR41149.ll
Index: llvm/test/CodeGen/WebAssembly/PR41149.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/WebAssembly/PR41149.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s
+
+; Regression test for PR41149.
+
+target triple = "wasm32-unknown--wasm"
+
+define void @mod() {
+entry:
+ %tmp = load <4 x i8>, <4 x i8>* undef
+ %tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
+ %tmp3 = sub <4 x i8> zeroinitializer, %tmp
+ %tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
+ store <4 x i8> %tmp4, <4 x i8>* undef
+ ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -68,6 +68,7 @@
case ISD::ZERO_EXTEND_VECTOR_INREG:
R = ScalarizeVecRes_VecInregOp(N);
break;
+ case ISD::ABS:
case ISD::ANY_EXTEND:
case ISD::BITREVERSE:
case ISD::BSWAP:
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