[PATCH] D59608: [AMDGPU] Fix clamp bit DAG operand
Michael Liao via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 12:42:20 PDT 2019
hliao created this revision.
Herald added subscribers: llvm-commits, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
hliao added reviewers: rampitec, arsenm, tpr.
- Should use `targetconstant` instead of `constant` operand for clamp bit, which is expected as an immediate operand. Under certain conditions, such as a common `i1 false` constant is used in other place and selected before the instruction with clamp bit, register operand may be added instead of immediate one. Use `targetcosntant` to enforce that.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D59608
Files:
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/test/CodeGen/AMDGPU/uaddo.ll
Index: llvm/test/CodeGen/AMDGPU/uaddo.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/uaddo.ll
+++ llvm/test/CodeGen/AMDGPU/uaddo.ll
@@ -170,6 +170,28 @@
ret void
}
+; FUNC-LABEL: {{^}}s_uaddo_clamp_bit:
+; GCN: v_add_{{i|u|co_u}}32_e32
+; GCN: s_endpgm
+define amdgpu_kernel void @s_uaddo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
+entry:
+ %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
+ %val = extractvalue { i32, i1 } %uadd, 0
+ %carry = extractvalue { i32, i1 } %uadd, 1
+ %c2 = icmp eq i1 %carry, false
+ %cc = icmp eq i32 %a, %b
+ br i1 %cc, label %exit, label %if
+
+if:
+ br label %exit
+
+exit:
+ %cout = phi i1 [false, %entry], [%c2, %if]
+ store i32 %val, i32 addrspace(1)* %out, align 4
+ store i1 %cout, i1 addrspace(1)* %carryout
+ ret void
+}
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
Index: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -931,9 +931,10 @@
unsigned Opc = N->getOpcode() == ISD::UADDO ?
AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
- CurDAG->SelectNodeTo(N, Opc, N->getVTList(),
- {N->getOperand(0), N->getOperand(1),
- CurDAG->getConstant(0, {}, MVT::i1)/*clamp bit*/});
+ CurDAG->SelectNodeTo(
+ N, Opc, N->getVTList(),
+ {N->getOperand(0), N->getOperand(1),
+ CurDAG->getTargetConstant(0, {}, MVT::i1) /*clamp bit*/});
}
void AMDGPUDAGToDAGISel::SelectFMA_W_CHAIN(SDNode *N) {
@@ -1041,7 +1042,8 @@
unsigned SubOp = AMDGPU::V_SUB_I32_e32;
if (Subtarget->hasAddNoCarry()) {
SubOp = AMDGPU::V_SUB_U32_e64;
- Opnds.push_back(Zero); // clamp bit
+ Opnds.push_back(
+ CurDAG->getTargetConstant(0, {}, MVT::i1)); // clamp bit
}
MachineSDNode *MachineSub =
@@ -1119,7 +1121,8 @@
unsigned SubOp = AMDGPU::V_SUB_I32_e32;
if (Subtarget->hasAddNoCarry()) {
SubOp = AMDGPU::V_SUB_U32_e64;
- Opnds.push_back(Zero); // clamp bit
+ Opnds.push_back(
+ CurDAG->getTargetConstant(0, {}, MVT::i1)); // clamp bit
}
MachineSDNode *MachineSub
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