[PATCH] D58964: [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel
David Stuttard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 20 02:29:26 PDT 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rL356540: [AMDGPU] Allow MIMG with no uses in adjustWritemask in isel (authored by dstuttard, committed by ).
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D58964/new/
https://reviews.llvm.org/D58964
Files:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll
Index: llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/img-nouse-adjust.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=amdgpu-isel -stop-after=amdgpu-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN
+
+; We're really just checking for no crashes
+; The feature we're testing for in AdjustWriteMask leaves the image_load as an instruction just post amdgpu-isel
+; In reality, it's hard to get an image intrinsic into AdjustWriteMask with no uses as it will usually get removed
+; first, but it can happen, hence the fix associated with this test
+
+; GCN-LABEL: name: _amdgpu_cs_main
+; GCN-LABEL: bb.0
+; GCN: IMAGE_LOAD_V4_V2
+define amdgpu_cs void @_amdgpu_cs_main(i32 %dummy) local_unnamed_addr #0 {
+.entry:
+ %unused.result = tail call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 0) #3
+ call void asm sideeffect ";", "" () #0
+ ret void
+}
+
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -9263,6 +9263,10 @@
// Don't allow 0 dmask, as hardware assumes one channel enabled.
bool NoChannels = !NewDmask;
if (NoChannels) {
+ if (!UsesTFC) {
+ // No uses of the result and not using TFC. Then do nothing.
+ return Node;
+ }
// If the original dmask has one channel - then nothing to do
if (OldBitsSet == 1)
return Node;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D58964.191461.patch
Type: text/x-patch
Size: 1926 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190320/0a523031/attachment.bin>
More information about the llvm-commits
mailing list