[PATCH] D59568: [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: samparker, SjoerdMeijer, olista01.
Herald added subscribers: kristof.beyls, javed.absar.
Herald added a project: LLVM.

This takes sequences like "mov r4, sp; str r0, [r4]", and optimizes them to something like "str r0, [sp]".

For regular stack variables, this optimization was already implemented: we lower loads and stores using frame indexes, which are expanded later. However, when constructing a call frame for a call with more than four arguments, the existing optimization doesn't apply.  We need to use stores which are actually relative to the current value of sp, and don't have an associated frame index.

This patch adds a special case to handle that construct.  At the DAG level, this is an ISD::STORE where the address is a CopyFromReg from SP (plus a small constant offset).

This applies only to Thumb1: in Thumb2 or ARM mode, a regular store instruction can access SP directly, so the COPY gets eliminated by existing code.

The change to ARMDAGToDAGISel::SelectThumbAddrModeSP is a related cleanup: we shouldn't pretend that it can select anything other than frame indexes.


Repository:
  rL LLVM

https://reviews.llvm.org/D59568

Files:
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  test/CodeGen/ARM/debug-frame.ll
  test/CodeGen/Thumb/frame-access.ll
  test/CodeGen/Thumb/pr35836_2.ll
  test/CodeGen/Thumb/thumb-shrink-wrapping.ll
  test/CodeGen/Thumb/umulo-128-legalisation-lowering.ll

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