[llvm] r356464 - [AMDGPU] Ban i8 min3 promotion.
Neil Henning via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 19 08:50:24 PDT 2019
Author: sheredom
Date: Tue Mar 19 08:50:24 2019
New Revision: 356464
URL: http://llvm.org/viewvc/llvm-project?rev=356464&view=rev
Log:
[AMDGPU] Ban i8 min3 promotion.
I found this really weird WWM-related case whereby through the WWM
transformations our isel lowering was trying to promote 2 min's into a
min3 for the i8 type, which our hardware doesn't support.
The new min3_i8.ll test case would previously spew the error:
PromoteIntegerResult #0: t69: i8 = SMIN3 t70, Constant:i8<0>, t68
Before the simple fix to our isel lowering to not do it for i8 MVT's.
Differential Revision: https://reviews.llvm.org/D59543
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll
llvm/trunk/test/CodeGen/AMDGPU/max3.ll
llvm/trunk/test/CodeGen/AMDGPU/min3.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=356464&r1=356463&r2=356464&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Tue Mar 19 08:50:24 2019
@@ -8137,10 +8137,10 @@ SDValue SITargetLowering::performMinMaxC
// Only do this if the inner op has one use since this will just increases
// register pressure for no benefit.
-
if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
- !VT.isVector() && VT != MVT::f64 &&
- ((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) {
+ !VT.isVector() &&
+ (VT == MVT::i32 || VT == MVT::f32 ||
+ ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->hasMin3Max3_16()))) {
// max(max(a, b), c) -> max3(a, b, c)
// min(min(a, b), c) -> min3(a, b, c)
if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
Modified: llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll?rev=356464&r1=356463&r2=356464&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fmin3.ll Tue Mar 19 08:50:24 2019
@@ -118,7 +118,33 @@ entry:
ret <2 x half> %res
}
+; GCN-LABEL: {{^}}test_fmin3_olt_0_f64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @test_fmin3_olt_0_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) #0 {
+ %a = load volatile double, double addrspace(1)* %aptr, align 4
+ %b = load volatile double, double addrspace(1)* %bptr, align 4
+ %c = load volatile double, double addrspace(1)* %cptr, align 4
+ %f0 = call double @llvm.minnum.f64(double %a, double %b)
+ %f1 = call double @llvm.minnum.f64(double %f0, double %c)
+ store double %f1, double addrspace(1)* %out, align 4
+ ret void
+}
+
+; Commute operand of second fmin
+; GCN-LABEL: {{^}}test_fmin3_olt_1_f64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @test_fmin3_olt_1_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) #0 {
+ %a = load volatile double, double addrspace(1)* %aptr, align 4
+ %b = load volatile double, double addrspace(1)* %bptr, align 4
+ %c = load volatile double, double addrspace(1)* %cptr, align 4
+ %f0 = call double @llvm.minnum.f64(double %a, double %b)
+ %f1 = call double @llvm.minnum.f64(double %c, double %f0)
+ store double %f1, double addrspace(1)* %out, align 4
+ ret void
+}
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
+declare double @llvm.minnum.f64(double, double) #1
declare float @llvm.minnum.f32(float, float) #1
declare half @llvm.minnum.f16(half, half) #1
declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
Modified: llvm/trunk/test/CodeGen/AMDGPU/max3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/max3.ll?rev=356464&r1=356463&r2=356464&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/max3.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/max3.ll Tue Mar 19 08:50:24 2019
@@ -88,6 +88,178 @@ define amdgpu_kernel void @v_test_umax3_
ret void
}
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i8:
+; SI: v_max3_i32
+
+; VI: v_max_i16
+; VI: v_max_i16
+
+; GFX9: v_max3_i16
+define amdgpu_kernel void @v_test_imax3_sgt_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+ %a = load i8, i8 addrspace(1)* %gep0
+ %b = load i8, i8 addrspace(1)* %gep1
+ %c = load i8, i8 addrspace(1)* %gep2
+ %icmp0 = icmp sgt i8 %a, %b
+ %i0 = select i1 %icmp0, i8 %a, i8 %b
+ %icmp1 = icmp sgt i8 %i0, %c
+ %i1 = select i1 %icmp1, i8 %i0, i8 %c
+ store i8 %i1, i8 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i8:
+; SI: v_max3_u32
+
+; VI: v_max_u16
+; VI: v_max_u16
+
+; GFX9: v_max3_u16
+define amdgpu_kernel void @v_test_umax3_ugt_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+ %a = load i8, i8 addrspace(1)* %gep0
+ %b = load i8, i8 addrspace(1)* %gep1
+ %c = load i8, i8 addrspace(1)* %gep2
+ %icmp0 = icmp ugt i8 %a, %b
+ %i0 = select i1 %icmp0, i8 %a, i8 %b
+ %icmp1 = icmp ugt i8 %i0, %c
+ %i1 = select i1 %icmp1, i8 %i0, i8 %c
+ store i8 %i1, i8 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i7:
+; SI: v_max3_i32
+
+; VI: v_max_i16
+; VI: v_max_i16
+
+; GFX9: v_max3_i16
+define amdgpu_kernel void @v_test_imax3_sgt_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+ %a = load i7, i7 addrspace(1)* %gep0
+ %b = load i7, i7 addrspace(1)* %gep1
+ %c = load i7, i7 addrspace(1)* %gep2
+ %icmp0 = icmp sgt i7 %a, %b
+ %i0 = select i1 %icmp0, i7 %a, i7 %b
+ %icmp1 = icmp sgt i7 %i0, %c
+ %i1 = select i1 %icmp1, i7 %i0, i7 %c
+ store i7 %i1, i7 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i7:
+; SI: v_max3_u32
+
+; VI: v_max_u16
+; VI: v_max_u16
+
+; GFX9: v_max3_u16
+define amdgpu_kernel void @v_test_umax3_ugt_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+ %a = load i7, i7 addrspace(1)* %gep0
+ %b = load i7, i7 addrspace(1)* %gep1
+ %c = load i7, i7 addrspace(1)* %gep2
+ %icmp0 = icmp ugt i7 %a, %b
+ %i0 = select i1 %icmp0, i7 %a, i7 %b
+ %icmp1 = icmp ugt i7 %i0, %c
+ %i1 = select i1 %icmp1, i7 %i0, i7 %c
+ store i7 %i1, i7 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i33:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_imax3_sgt_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+ %a = load i33, i33 addrspace(1)* %gep0
+ %b = load i33, i33 addrspace(1)* %gep1
+ %c = load i33, i33 addrspace(1)* %gep2
+ %icmp0 = icmp sgt i33 %a, %b
+ %i0 = select i1 %icmp0, i33 %a, i33 %b
+ %icmp1 = icmp sgt i33 %i0, %c
+ %i1 = select i1 %icmp1, i33 %i0, i33 %c
+ store i33 %i1, i33 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i33:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_umax3_ugt_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+ %a = load i33, i33 addrspace(1)* %gep0
+ %b = load i33, i33 addrspace(1)* %gep1
+ %c = load i33, i33 addrspace(1)* %gep2
+ %icmp0 = icmp ugt i33 %a, %b
+ %i0 = select i1 %icmp0, i33 %a, i33 %b
+ %icmp1 = icmp ugt i33 %i0, %c
+ %i1 = select i1 %icmp1, i33 %i0, i33 %c
+ store i33 %i1, i33 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imax3_sgt_i64:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_imax3_sgt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+ %a = load i64, i64 addrspace(1)* %gep0
+ %b = load i64, i64 addrspace(1)* %gep1
+ %c = load i64, i64 addrspace(1)* %gep2
+ %icmp0 = icmp sgt i64 %a, %b
+ %i0 = select i1 %icmp0, i64 %a, i64 %b
+ %icmp1 = icmp sgt i64 %i0, %c
+ %i1 = select i1 %icmp1, i64 %i0, i64 %c
+ store i64 %i1, i64 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umax3_ugt_i64:
+; GCN-NOT: v_max3
+define amdgpu_kernel void @v_test_umax3_ugt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+ %a = load i64, i64 addrspace(1)* %gep0
+ %b = load i64, i64 addrspace(1)* %gep1
+ %c = load i64, i64 addrspace(1)* %gep2
+ %icmp0 = icmp ugt i64 %a, %b
+ %i0 = select i1 %icmp0, i64 %a, i64 %b
+ %icmp1 = icmp ugt i64 %i0, %c
+ %i1 = select i1 %icmp1, i64 %i0, i64 %c
+ store i64 %i1, i64 addrspace(1)* %out
+ ret void
+}
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind }
Modified: llvm/trunk/test/CodeGen/AMDGPU/min3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/min3.ll?rev=356464&r1=356463&r2=356464&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/min3.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/min3.ll Tue Mar 19 08:50:24 2019
@@ -158,6 +158,178 @@ define amdgpu_kernel void @v_test_umin3_
ret void
}
+; GCN-LABEL: {{^}}v_test_imin3_slt_i8:
+; SI: v_min3_i32
+
+; VI: v_min_i16
+; VI: v_min_i16
+
+; GFX9: v_min3_i16
+define amdgpu_kernel void @v_test_imin3_slt_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+ %a = load i8, i8 addrspace(1)* %gep0
+ %b = load i8, i8 addrspace(1)* %gep1
+ %c = load i8, i8 addrspace(1)* %gep2
+ %icmp0 = icmp slt i8 %a, %b
+ %i0 = select i1 %icmp0, i8 %a, i8 %b
+ %icmp1 = icmp slt i8 %i0, %c
+ %i1 = select i1 %icmp1, i8 %i0, i8 %c
+ store i8 %i1, i8 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i8:
+; SI: v_min3_u32
+
+; VI: v_min_u16
+; VI: v_min_u16
+
+; GFX9: v_min3_u16
+define amdgpu_kernel void @v_test_umin3_ult_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr, i8 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i8, i8 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid
+ %a = load i8, i8 addrspace(1)* %gep0
+ %b = load i8, i8 addrspace(1)* %gep1
+ %c = load i8, i8 addrspace(1)* %gep2
+ %icmp0 = icmp ult i8 %a, %b
+ %i0 = select i1 %icmp0, i8 %a, i8 %b
+ %icmp1 = icmp ult i8 %i0, %c
+ %i1 = select i1 %icmp1, i8 %i0, i8 %c
+ store i8 %i1, i8 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imin3_slt_i7:
+; SI: v_min3_i32
+
+; VI: v_min_i16
+; VI: v_min_i16
+
+; GFX9: v_min3_i16
+define amdgpu_kernel void @v_test_imin3_slt_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+ %a = load i7, i7 addrspace(1)* %gep0
+ %b = load i7, i7 addrspace(1)* %gep1
+ %c = load i7, i7 addrspace(1)* %gep2
+ %icmp0 = icmp slt i7 %a, %b
+ %i0 = select i1 %icmp0, i7 %a, i7 %b
+ %icmp1 = icmp slt i7 %i0, %c
+ %i1 = select i1 %icmp1, i7 %i0, i7 %c
+ store i7 %i1, i7 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i7:
+; SI: v_min3_u32
+
+; VI: v_min_u16
+; VI: v_min_u16
+
+; GFX9: v_min3_u16
+define amdgpu_kernel void @v_test_umin3_ult_i7(i7 addrspace(1)* %out, i7 addrspace(1)* %aptr, i7 addrspace(1)* %bptr, i7 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i7, i7 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i7, i7 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i7, i7 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i7, i7 addrspace(1)* %out, i32 %tid
+ %a = load i7, i7 addrspace(1)* %gep0
+ %b = load i7, i7 addrspace(1)* %gep1
+ %c = load i7, i7 addrspace(1)* %gep2
+ %icmp0 = icmp ult i7 %a, %b
+ %i0 = select i1 %icmp0, i7 %a, i7 %b
+ %icmp1 = icmp ult i7 %i0, %c
+ %i1 = select i1 %icmp1, i7 %i0, i7 %c
+ store i7 %i1, i7 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imin3_slt_i33:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_imin3_slt_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+ %a = load i33, i33 addrspace(1)* %gep0
+ %b = load i33, i33 addrspace(1)* %gep1
+ %c = load i33, i33 addrspace(1)* %gep2
+ %icmp0 = icmp slt i33 %a, %b
+ %i0 = select i1 %icmp0, i33 %a, i33 %b
+ %icmp1 = icmp slt i33 %i0, %c
+ %i1 = select i1 %icmp1, i33 %i0, i33 %c
+ store i33 %i1, i33 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i33:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_umin3_ult_i33(i33 addrspace(1)* %out, i33 addrspace(1)* %aptr, i33 addrspace(1)* %bptr, i33 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i33, i33 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i33, i33 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i33, i33 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i33, i33 addrspace(1)* %out, i32 %tid
+ %a = load i33, i33 addrspace(1)* %gep0
+ %b = load i33, i33 addrspace(1)* %gep1
+ %c = load i33, i33 addrspace(1)* %gep2
+ %icmp0 = icmp ult i33 %a, %b
+ %i0 = select i1 %icmp0, i33 %a, i33 %b
+ %icmp1 = icmp ult i33 %i0, %c
+ %i1 = select i1 %icmp1, i33 %i0, i33 %c
+ store i33 %i1, i33 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_imin3_slt_i64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_imin3_slt_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+ %a = load i64, i64 addrspace(1)* %gep0
+ %b = load i64, i64 addrspace(1)* %gep1
+ %c = load i64, i64 addrspace(1)* %gep2
+ %icmp0 = icmp slt i64 %a, %b
+ %i0 = select i1 %icmp0, i64 %a, i64 %b
+ %icmp1 = icmp slt i64 %i0, %c
+ %i1 = select i1 %icmp1, i64 %i0, i64 %c
+ store i64 %i1, i64 addrspace(1)* %outgep
+ ret void
+}
+
+; GCN-LABEL: {{^}}v_test_umin3_ult_i64:
+; GCN-NOT: v_min3
+define amdgpu_kernel void @v_test_umin3_ult_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i64 addrspace(1)* %cptr) #0 {
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
+ %gep1 = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
+ %gep2 = getelementptr i64, i64 addrspace(1)* %cptr, i32 %tid
+ %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
+ %a = load i64, i64 addrspace(1)* %gep0
+ %b = load i64, i64 addrspace(1)* %gep1
+ %c = load i64, i64 addrspace(1)* %gep2
+ %icmp0 = icmp ult i64 %a, %b
+ %i0 = select i1 %icmp0, i64 %a, i64 %b
+ %icmp1 = icmp ult i64 %i0, %c
+ %i1 = select i1 %icmp1, i64 %i0, i64 %c
+ store i64 %i1, i64 addrspace(1)* %outgep
+ ret void
+}
+
declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind }
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