[PATCH] D59295: [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure.

[Neil Henning via Phabricator via llvm-commits]

sheredom marked 6 inline comments as done.
sheredom added inline comments.


================
Comment at: lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp:222-227
+      if (MI.getOpcode() == AMDGPU::S_OR_SAVEEXEC_B64 &&
+          MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == -1) {
+        LLVM_DEBUG(dbgs() << "entering WWM region: " << MI << "\n");
+        InWWM = true;
+        continue;
+      }
----------------
cwabbott wrote:
> arsenm wrote:
> > I don't like this hardcoded opcode check. Why is S_OR_SAVEEXEC_B64 special?
> IIRC I wrote this since WholeQuadMode currently just emits a S_OR_SAVEEXEC_B64 foo, -1 in order to start WWM, so you have to check it manually in order to know when WWM starts. Maybe it's better to got back and add a ENTER_WWM pseudoinstruction like the pre-existing EXIT_WWM.
I've added an ENTER_WWM like was suggested!


================
Comment at: test/CodeGen/AMDGPU/wwm-reserved.ll:57
+}
+
+declare i32 @llvm.amdgcn.wwm.i32(i32)
----------------
arsenm wrote:
> Needs some cases with control flow
Added a CFG and a called function case.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59295/new/

https://reviews.llvm.org/D59295