[llvm] r356358 - [RISCV] Add ImmArg to intrinsics

[Alex Bradbury via llvm-commits]

Author: asb
Date: Sun Mar 17 23:01:27 2019
New Revision: 356358

URL: http://llvm.org/viewvc/llvm-project?rev=356358&view=rev
Log:
[RISCV] Add ImmArg to intrinsics

Modified:
    llvm/trunk/include/llvm/IR/IntrinsicsRISCV.td

Modified: llvm/trunk/include/llvm/IR/IntrinsicsRISCV.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsRISCV.td?rev=356358&r1=356357&r2=356358&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsRISCV.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsRISCV.td Sun Mar 17 23:01:27 2019
@@ -18,13 +18,13 @@ let TargetPrefix = "riscv" in {
 class MaskedAtomicRMW32Intrinsic
     : Intrinsic<[llvm_i32_ty],
                 [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
-                [IntrArgMemOnly, NoCapture<0>]>;
+                [IntrArgMemOnly, NoCapture<0>, ImmArg<3>]>;
 
 class MaskedAtomicRMW32WithSextIntrinsic
     : Intrinsic<[llvm_i32_ty],
                 [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
                  llvm_i32_ty],
-                [IntrArgMemOnly, NoCapture<0>]>;
+                [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
 
 def int_riscv_masked_atomicrmw_xchg_i32 : MaskedAtomicRMW32Intrinsic;
 def int_riscv_masked_atomicrmw_add_i32  : MaskedAtomicRMW32Intrinsic;
@@ -38,18 +38,18 @@ def int_riscv_masked_atomicrmw_umin_i32
 def int_riscv_masked_cmpxchg_i32
     : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty,
                                 llvm_i32_ty, llvm_i32_ty],
-                [IntrArgMemOnly, NoCapture<0>]>;
+                [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
 
 class MaskedAtomicRMW64Intrinsic
     : Intrinsic<[llvm_i64_ty],
                 [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
-                [IntrArgMemOnly, NoCapture<0>]>;
+                [IntrArgMemOnly, NoCapture<0>, ImmArg<3>]>;
 
 class MaskedAtomicRMW64WithSextIntrinsic
     : Intrinsic<[llvm_i64_ty],
                 [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
                  llvm_i64_ty],
-                [IntrArgMemOnly, NoCapture<0>]>;
+                [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
 
 def int_riscv_masked_atomicrmw_xchg_i64 : MaskedAtomicRMW64Intrinsic;
 def int_riscv_masked_atomicrmw_add_i64  : MaskedAtomicRMW64Intrinsic;
@@ -63,6 +63,6 @@ def int_riscv_masked_atomicrmw_umin_i64
 def int_riscv_masked_cmpxchg_i64
     : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty,
                                 llvm_i64_ty, llvm_i64_ty],
-                [IntrArgMemOnly, NoCapture<0>]>;
+                [IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
 
 } // TargetPrefix = "riscv"