[PATCH] D59479: [X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, andreadb.
Herald added a project: LLVM.

This patch enables the use of lowerShuffleAsBitMask for 512-bit blends before
falling back to move immedate, GPR to k-register, and masked op.

I had to make some changes to support v8i64 when i64 is not a legal type. And to
support floating point types.

This trades a load for the move immediate and GPR move which is higher latency.
But its probably better for register pressure not having to hop through other
register classes. The load+and should play better with LICM and
rematerialization I think.


Repository:
  rL LLVM

https://reviews.llvm.org/D59479

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx512-mask-op.ll
  test/CodeGen/X86/merge-consecutive-loads-512.ll
  test/CodeGen/X86/vector-shuffle-512-v32.ll

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